US2019279974A1PendingUtilityA1

Semiconductor Devices and Methods of Manufacture Thereof

Assignee: TAIWAN SEMICONDUCTOR MFG CO LTDPriority: Dec 26, 2013Filed: May 23, 2019Published: Sep 12, 2019
Est. expiryDec 26, 2033(~7.4 yrs left)· nominal 20-yr term from priority
H10W 20/0238H10W 20/2134H10W 20/2125H10W 20/0242H10W 20/0234H10W 20/0253H10W 99/00H10W 90/26H10W 90/297H10W 72/874H10W 72/853H10W 70/093H10W 80/312H10W 80/327H10W 80/301H10W 90/22H10W 70/60H10W 90/792H10W 20/20H10W 20/023H10W 20/083H10W 90/00H01L 24/82H01L 2224/80895H01L 2924/0002H01L 2224/2405H01L 2224/82947H01L 24/92H01L 25/0657H01L 2224/9202H01L 21/76898H01L 2224/80894H01L 2225/06565H01L 23/481H01L 2224/73251H01L 24/24H01L 2924/00014H01L 24/73H01L 2224/245H01L 2224/9222H01L 2224/08145H01L 2225/06544H01L 2224/82931H01L 21/76805H01L 2224/80896H01L 24/08H01L 2224/73201H01L 2224/9212H01L 2224/24146H01L 2224/82106H01L 24/80H01L 2224/24147H01L 2224/82101H01L 25/50H10W 20/031H10D 64/01304
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Claims

Abstract

Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a first semiconductor chip including a first substrate and a first conductive feature formed over the first substrate, and a second semiconductor chip bonded to the first semiconductor chip. The second semiconductor chip includes a second substrate and a second conductive feature formed over the second substrate. A conductive plug is disposed through the first conductive feature and is coupled to the second conductive feature. The conductive plug includes a first portion disposed over the first conductive feature, the first portion having a first width, and a second portion disposed beneath or within the first conductive feature. The second portion has a second width. The first width is greater than the second width.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first semiconductor chip comprising a first substrate and a first conductive feature on the first substrate;   a second semiconductor chip bonded to the first semiconductor chip, the second semiconductor chip comprising a second substrate and a second conductive feature on the second substrate, the second conductive feature is directly bonded to the first conductive feature at an interface between the first semiconductor chip and the second semiconductor chip; and   a conductive plug disposed through the first semiconductor chip and coupled to the second conductive feature, wherein the conductive plug comprises:
 a first portion disposed over the first conductive feature, the first portion comprising a first width; 
 a second portion disposed at least partially within the first conductive feature, the second portion comprising a second width, the first width is greater than the second width; and 
 a third portion within the first conductive feature, the third portion extending from the second portion to the second conductive feature, the third portion comprising a third width, and the second width is greater than the third width. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first semiconductor chip comprises a plurality of dielectric layers, the first conductive feature being disposed in the plurality of dielectric layers, the second portion of the conductive plug being disposed at least partially in the plurality of dielectric layers. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first portion of the conductive plug is disposed in the first substrate. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the first conductive feature is wider than the second conductive feature. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising a dielectric liner over the first substrate and along sidewalls of the first portion of the conductive plug, a portion of the dielectric liner extending under a bottom surface of the first portion of the conductive plug. 
     
     
         6 . The semiconductor device of  claim 5 , further comprising a bottom anti-reflection coating (BARC) layer between the dielectric liner and the first substrate. 
     
     
         7 . The semiconductor device of  claim 5 , wherein the dielectric liner is not disposed along sidewalls of at least a portion of the second portion of the conductive plug. 
     
     
         8 . The semiconductor device of  claim 5 , further comprising a passivation layer over the dielectric liner.

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