Delay modulated clock division

Abstract

A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

What is claimed is: 
     
         1 . A clock divider, comprising:
 a clock delay line comprising a plurality of delay elements;   a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements; and   a bit pattern source coupled to the clock delay selector,   wherein the clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.   
     
     
         2 . The clock divider of  claim 1 , wherein the bit pattern source is a bit pattern generator. 
     
     
         3 . The clock divider of  claim 1 , wherein the bit pattern source is a bit pattern storage element configured to store a pre-defined bit pattern. 
     
     
         4 . The clock divider of  claim 1 , further comprising a second bit pattern source and a multiplexer, wherein the bit pattern source is coupled to a first input of the multiplexer, the second bit pattern source is coupled to a second input of the multiplexer, and an output of the multiplexer is coupled to the clock delay selector. 
     
     
         5 . The clock divider of  claim 1 , wherein the clock delay line is configured to:
 receive a division factor and a clock signal;   receive a delay element selection signal from the clock delay selector; and   modulate the clock signal according to the clock delay selector to form the modulated divided clock signal with the suppressed fundamental spectral component.   
     
     
         6 . The clock divider of  claim 5 , wherein the clock delay selector generates the delay element selection signal according to one or more bits of a binary sequence received from the bit pattern source. 
     
     
         7 . A radio frequency (RF) sampling receiver, comprising:
 a RF sampling analog-to-digital converter (ADC) configured to sample an RF signal at a sampling rate to form a sampled signal;   a clock generator coupled to the RF sampling ADC and configured to generate a root clock signal at the sampling rate for use by the RF sampling ADC in sampling the RF signal;   a clock divider configured to divide the root clock signal according to delay modulated clock division to form a modulated divided clock signal; and   digital logic coupled to the RF sampling ADC and the clock divider and configured to process the sampled signal at a frequency of the modulated divided clock signal.