High-linearity cmos wifi rf power amplifiers in wide range of burst signals

Abstract

An RF power amplifier biasing circuit has a start ramp signal input, a main current source input, an auxiliary current source input, and a circuit output. A ramp-up capacitor is connected to the auxiliary current source input. A ramp-up switch transistor is connected to the start ramp signal input and is selectively thereby to connect the auxiliary current source input to the ramp-up capacitor. A buffer stage has an input connected to the ramp-up capacitor and an output connected to the main current source input at a sum node. A mirror transistor has a gate terminal corresponding to the circuit output and a source terminal connected to the sum node and to the gate terminal.

1 - 26 . (canceled) 
     
     
         27 . A radio frequency power amplifier circuit comprising:
 a power amplifier with an output and a radio frequency signal input; and   a bias control circuit connected to the power amplifier, the bias control circuit being connected to a main current source generating a constant current during an input signal burst to bias the power amplifier, and to an auxiliary current source generating a constant current, the auxiliary current source being selectively summed with the main current source in a linearly dependent relationship to the input signal burst.   
     
     
         28 . The radio frequency power amplifier circuit of  claim 27  wherein the bias control circuit includes a ramp-up capacitor connected to the auxiliary current source, the ramp-up capacitor being charged in the linearly dependent relationship to the input signal burst. 
     
     
         29 . The radio frequency power amplifier circuit of  claim 28  wherein the bias control circuit further includes a ramp-up switch connected to the auxiliary current source, the ramp-up capacitor being charged in response to the ramp-up switch receiving a ramp start signal input corresponding to the input signal burst. 
     
     
         30 . The radio frequency power amplifier circuit of  claim 29  wherein the ramp-up switch is a transistor with a gate receptive to the ramp start signal input and a drain being connected to the auxiliary current source. 
     
     
         31 . The radio frequency power amplifier circuit of  claim 28  wherein the bias control circuit includes a ramp-down switch connected to the ramp-up capacitor, the ramp-down switch being selectively activated at an end of the input signal burst to discharge the ramp-up capacitor. 
     
     
         32 . The radio frequency power amplifier circuit of  claim 31  wherein the ramp-down switch is deactivated at the end of the input signal burst. 
     
     
         33 . The radio frequency power amplifier circuit of  claim 31  wherein the ramp-down switch is discharged in response to the ramp-down switch receiving a stop ramp signal input. 
     
     
         34 . The radio frequency power amplifier circuit of  claim 28  wherein the bias control circuit includes a capacitor discharge resistor connected to the ramp-up capacitor. 
     
     
         35 . The radio frequency power amplifier circuit of  claim 34  wherein the bias control circuit includes a buffer with an input connected to the ramp-up capacitor. 
     
     
         36 . The radio frequency power amplifier circuit of  claim 35  wherein the bias control circuit includes an inverter, the inverter including an inverter input connected to the ramp-up capacitor and an inverter output connected to the buffer, voltage at the inverter input exponentially decaying in a duration less than a minimum input signal burst duration. 
     
     
         37 . The radio frequency power amplifier circuit of  claim 36  wherein values of the ramp-up capacitor and the capacitor discharge resistor correspond to a specific exponential decay of the voltage at the input of the inverter. 
     
     
         38 . The radio frequency power amplifier circuit of  claim 35  wherein the bias control circuit includes a mirror circuit connected to the power amplifier and to the buffer, the mirror circuit being biased with the main current source. 
     
     
         39 . A radio frequency power amplifier biasing circuit connectible to an enable line input, a first reference voltage, and a second reference voltage, the circuit comprising:
 a closed loop operational amplifier circuit having an input and an output, the output defining a biasing output of the radio frequency power amplifier biasing circuit; and   a switch operable by a signal on the enable line input to selectively connect the first reference voltage and the second reference voltage to the input of the closed loop operational amplifier via a resistor-capacitor network, the resistor-capacitor network defining a time constant for switching from the first reference voltage to the second reference voltage.   
     
     
         40 . The radio frequency power amplifier biasing circuit of  claim 39  wherein the closed loop operational amplifier circuit includes an operational amplifier and an output transistor, the output transistor connected to an output of the operational amplifier and having an output that defines the biasing output of the radio frequency power amplifier biasing circuit and connects to a feedback input of the operational amplifier via a voltage divider. 
     
     
         41 . The radio frequency power amplifier biasing circuit of  claim 40  wherein the output transistor is a PMOS type transistor defined by a gate, a source, and a drain, the gate being connected to the output of the operational amplifier and the drain defining the biasing output of the radio frequency power amplifier biasing circuit and being connected to the feedback input of the operational amplifier via the voltage divider. 
     
     
         42 . The radio frequency power amplifier biasing circuit of  claim 39  further comprising a band gap reference circuit whose output defines the first reference voltage and the second reference voltage. 
     
     
         43 . The radio frequency power amplifier biasing circuit of  claim 42  wherein the first reference voltage and the second reference voltage are further defined by a first reference voltage resistor and a second reference voltage resistor. 
     
     
         44 . The radio frequency power amplifier biasing circuit of  claim 42  wherein the closed loop operational amplifier circuit is powered by the band gap reference circuit. 
     
     
         45 . The radio frequency power amplifier biasing circuit of  claim 42  wherein the output of the band gap reference circuit is adjustable in response to measured ambient temperature. 
     
     
         46 . The radio frequency power amplifier biasing circuit of  claim 39  wherein the switch has a first throw terminal connected to the first reference voltage, a second throw terminal connected to the second reference voltage, and a pole terminal connected to the resistor-capacitor network, the switch selectively connecting the first throw terminal and the second throw terminal to the pole terminal in response to the signal on the enable line input.