US2019267476A1PendingUtilityA1

Back-channel-etched tft substrate and manufacturing method thereof

Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECH CO LTDPriority: Nov 21, 2017Filed: May 10, 2019Published: Aug 29, 2019
Est. expiryNov 21, 2037(~11.3 yrs left)· nominal 20-yr term from priority
Inventors:Chunsheng Jiang
H10P 95/70H10P 52/00H10P 50/667H10P 50/20H10P 14/3434H10P 14/3426H10P 14/3238H10P 50/00H10P 14/265H01L 21/3213H01L 29/45H01L 27/1274H01L 27/1262H01L 21/02628H01L 29/66969H10D 30/6757H10D 86/0223H10D 86/0212H10D 64/62H10D 62/405H10D 30/6755H10D 86/60H10D 86/411H10D 99/00H10D 86/021
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Claims

Abstract

The invention provides a BCE TFT substrate and manufacturing method thereof. The method comprises forming a first IGZO thin film with polycrystalline IGZO particles in a predetermined area of active layer before sputtering IGZO, the polycrystalline IGZO particles in the first IGZO thin film used as seed crystal during sputtering to grow a C-axis crystallized IGZO in good crystalline state to form a second IGZO thin film. The first and second IGZO thin films form an active layer. Because the surface of the active layer is presented as C-axis crystallized IGZO, the active layer is not damaged by the copper etchant during etching source and drain so as to ensure stable performance of active layer and to avoid the development of special copper etching solution. As such, the BCE TFT substrate has stable electrical performance. The BCE TFT substrate manufactured by the above manufacturing method has stable electrical performance.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A back-channel-etched (BCE) thin film transistor (TFT) substrate, comprising: a base substrate, a gate disposed on the base substrate, a gate insulating layer disposed on the base substrate and the gate, an active layer disposed on the gate insulating layer and corresponding to the above of the gate, a source and a drain separated with interval and disposed on the active layer and the gate insulating layer, a passivation layer disposed on the source, the drain, and the active layer, and a pixel electrode disposed on the passivation layer;
 a via being disposed on the passivation layer and corresponding to the above of the drain, the pixel electrode contacting with the drain through the via;   the active layer comprising the first IGZO thin film on the gate insulating layer and the second IGZO thin film on the first IGZO thin film; the first IGZO thin film being presented as a thin film formed by polycrystalline IGZO particles; the second IGZO thin film being presented as a C-axis crystallized IGZO thin film.   
     
     
         2 . The BCE TFT substrate as claimed in  claim 1 , wherein the material of the gate, the source and the drain is copper; the material of the pixel electrode is indium tin oxide (ITO).

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