Extended contact area using undercut silicide extensions

Abstract

The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a source-drain (S-D) region of a field effect transistor (FET) having extensions by using an undercut etch and a salicide process. A method of forming a contact silicide extension is disclosed. The method may include: forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending below the dielectric layer to a gate spacer formed on a sidewall of a gate stack; and forming a contact silicide in the undercut region, the contact silicide in direct contact with the source-drain region.

What is claimed is: 
     
         1 . A method of forming a contact silicide extension comprising:
 forming an undercut region below a dielectric layer and above a source-drain region, the undercut region located directly below a bottom of a contact trench and extending laterally below the dielectric layer to a gate spacer formed on a sidewall of a gate stack wherein forming the undercut region below the dielectric layer and above the source-drain region comprises:
 forming a liner layer on the gate spacer and the source-drain region; 
 forming the dielectric layer above the liner layer; 
 forming the contact trench in the dielectric layer to expose an upper surface of the liner layer; and 
 removing a portion of the liner layer directly beneath the dielectric layer. 
   
     
     
         2 . The method of  claim 1 , wherein forming the liner layer comprises:
 forming the liner layer directly above a gate stack.   
     
     
         3 . The method of  claim 1 , wherein removing the portion of the liner layer comprises:
 performing an isotropic wet etching process to remove the portion of the liner layer selective to the dielectric layer, the source-drain region, and the gate spacer.   
     
     
         4 . The method of  claim 1 , wherein removing the portion of the liner layer comprises:
 performing an anisotropic etching process to remove a portion of an etch stop layer selective to the dielectric layer and the liner layer.   
     
     
         5 . The method of  claim 1 , wherein removing the portion of the liner layer comprises:
 performing an anisotropic etching process to remove a portion of an etch stop layer selective to the dielectric layer and the liner layer,   performing an isotropic wet etching process to remove the portion of the liner layer selective to the dielectric layer, the etch stop layer, the source-drain region, and the gate spacer.   
     
     
         6 . The method of  claim 1 , further comprising:
 forming a contact silicide in the undercut region, the contact silicide being in direct contact with the source-drain region.   
     
     
         7 . The method of  claim 1 , further comprising:
 depositing a metal layer in the undercut region; and   performing an annealing process to cause the metal layer to react with silicon in the source-drain region to form a silicide.   
     
     
         8 . The method of  claim 1 , further comprising:
 forming an electrical contact in the contact trench and on the contact silicide.   
     
     
         9 . A method comprising:
 forming a conformal liner on a source-drain region and along a vertical sidewall of a gate spacer;   forming an etch stop layer on the conformal liner;   forming a contact trench in a dielectric layer, a bottom of the contact trench exposing a top surface of a portion of the conformal liner; and   removing a portion of the conformal liner below the contact trench to form an undercut region, the undercut region extending laterally from the bottom of the contact trench directly below the etch stop layer.   
     
     
         10 . The method of  claim 9 , wherein the source-drain region comprises a doped epitaxial semiconductor material on a semiconductor substrate. 
     
     
         11 . The method of  claim 9 , wherein forming the conformal liner on the source-drain region comprises:
 depositing a metal nitride layer.   
     
     
         12 . The method of  claim 9 , wherein forming the contact trench in the dielectric layer comprises:
 removing a portion of the etch stop layer at a bottom of the contact trench selective to the dielectric layer and the liner layer using an anisotropic etching process.   
     
     
         13 . The method of  claim 9 , wherein removing the portion of the liner below the contact trench to form the undercut region comprises:
 removing the portion of the liner selective to the dielectric layer, the source-drain region, and the gate spacer using an isotropic wet etching process.   
     
     
         14 . The method of  claim 9 , further comprising:
 forming a contact silicide in the undercut region, the contact silicide being in direct contact with the source-drain region.   
     
     
         15 . The method of  claim 9 , further comprising:
 depositing a metal layer in the undercut region; and   performing an annealing process to cause the metal layer to react with silicon in the source-drain region to form a silicide.   
     
     
         16 . The method of  claim 9 , further comprising:
 forming an electrical contact in the contact trench and on the contact silicide.   
     
     
         17 . A method comprising:
 forming a conformal layer on a source-drain region and along a vertical sidewall of a gate spacer;   forming a contact trench in a dielectric layer above the conformal layer, a bottom of the contact trench exposing a portion of the conformal layer; and   removing a portion of the conformal layer below the contact trench to form an undercut region, the undercut region extending laterally from the bottom of the contact trench.   
     
     
         18 . The method of  claim 17 , wherein removing the portion of the conformal layer below the contact trench to form the undercut region comprises:
 removing the portion of the conformal layer selective to the dielectric layer, the source-drain region, and the gate spacer using an isotropic wet etching process.   
     
     
         19 . The method of  claim 17 , further comprising:
 forming a contact silicide in the undercut region, the contact silicide being in direct contact with the source-drain region.   
     
     
         20 . The method of  claim 17 , further comprising:
 depositing a metal layer in the undercut region; and   performing an annealing process to cause the metal layer to react with silicon in the source-drain region.