Barrier layer for interconnects in 3d integrated device

Abstract

An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on. A high-temperature treatment and functional testing of the vertically integrated electronic device may be conducted after each stack sequence.

What is claimed is: 
     
         1 . An electronic device comprising:
 a substrate;   a plurality of electrically conductive traces disposed on at least a portion of the substrate;   a plurality of barrier layers, each respective barrier layer of the plurality of barrier layers completely overlying each respective electrically conductive trace of the plurality of electrically conductive traces;   a plurality of electrically conductive interconnects, each respective electrically conductive interconnect of the plurality of electrically conductive interconnects at least partially overlying each respective barrier layer of the plurality of barrier layers; and   a bonding layer at least partially surrounding the plurality of electrically conductive interconnects,   wherein each respective barrier layer of the plurality of barrier layers is interposed between each respective electrically conductive trace of the plurality of electrically conductive traces and each respective electrically conductive interconnect of the plurality of electrically conductive interconnects.   
     
     
         2 . The electronic device according to  claim 1 ,
 wherein each of the plurality of barrier layers is a planar barrier layer; and   wherein each respective electrically conductive interconnect of the plurality of electrically conductive interconnects extends upright relative to each respective planar barrier layer of the plurality of barrier layers.   
     
     
         3 . The electronic device according to  claim 1 ,
 wherein the bonding layer at least partially overlies the plurality of electrically conductive traces, and at least partially overlies the plurality of barrier layers.   
     
     
         4 . The electronic device according to  claim 1 ,
 wherein the bonding layer completely surrounds the plurality of electrically conductive interconnects.   
     
     
         5 . The electronic device according to  claim 1 ,
 wherein each of the plurality of electrically conductive traces is made from a first metallic material;   wherein each of the plurality of electrically conductive interconnects is made from a second metallic material that is different from the first metallic material; and   wherein each respective barrier layer of the plurality of barrier layers is configured to prevent interdiffusion between each respective electrically conductive trace of the plurality of electrically conductive traces and each respective electrically conductive interconnect of the plurality of electrically conductive interconnects.   
     
     
         6 . The electronic device according to  claim 1 ,
 wherein each of the plurality of electrically conductive interconnects is made from a transition metal.   
     
     
         7 . The electronic device according to  claim 6 ,
 wherein each of the plurality of electrically conductive interconnects is made from nickel or nickel alloy.   
     
     
         8 . The electronic device according to  claim 1 ,
 wherein each of the plurality of electrically conductive traces is made from aluminum or aluminum alloy.   
     
     
         9 . The electronic device according to  claim 1 ,
 wherein each of the plurality of barrier layers is made from: titanium nitride, titanium tungsten, tantalum, or tantalum nitride.   
     
     
         10 . The electronic device according to  claim 1 ,
 wherein the bonding layer is made from a non-metallic oxide.   
     
     
         11 . The electronic device according to  claim 10 ,
 wherein the bonding layer is made from silicon dioxide.   
     
     
         12 . The electronic device according to  claim 1 ,
 wherein the plurality of barrier layers are configured to accept formation of respective seed layers thereon, the seed layers being compatible with the plurality of electrically conductive interconnects such that the seed layers form respective integral portions of the plurality of electrically conductive interconnects.   
     
     
         13 . The electronic device according to  claim 1 ,
 wherein each of the plurality of electrically conductive traces is formed by physical vapor deposition, chemical vapor deposition, vapor phase deposition, or sputtering;   wherein each of the plurality of barrier layers is formed by physical vapor deposition, chemical vapor deposition, vapor phase deposition, or sputtering;   wherein each of the plurality of electrically conductive interconnects is formed by physical vapor deposition, chemical vapor deposition, sputtering, or electroplating; and   wherein the bonding layer is formed by chemical vapor deposition, sputtering, spin-on glass process, or plasma enhanced CVD.   
     
     
         14 . The electronic device according to  claim 1 ,
 wherein the plurality of electrically conductive interconnects is a first a plurality of electrically conductive interconnects; and   wherein the bonding layer is a first bonding layer;   the electronic device further comprising:
 a second substrate; 
 a second plurality of electrically conductive traces disposed on at least a portion of the second substrate; 
 a second plurality of barrier layers, each respective second barrier layer of the second plurality of barrier layers at least partially overlying each respective second electrically conductive trace of the second plurality of electrically conductive traces; 
 a second plurality of electrically conductive interconnects, each respective second electrically conductive interconnect of the second plurality of electrically conductive interconnects at least partially overlying each respective second barrier layer of the second plurality of barrier layers; and 
 a second bonding layer at least partially overlying the second plurality of electrically conductive traces and at least partially overlying the second plurality of barrier layers, the second bonding layer at least partially surrounding the second plurality of electrically conductive interconnects, 
 wherein each respective second barrier layer of the second plurality of barrier layers is interposed between each respective second electrically conductive trace of the second plurality of electrically conductive traces and each respective second electrically conductive interconnect of the second plurality of electrically conductive interconnects, and 
   wherein the first bonding layer is bonded to the second bonding layer, and   wherein at least one of the first plurality of electrically conductive interconnects is diffusion bonded to at least one of the second plurality of electrically conductive interconnects.   
     
     
         15 . An electronic device comprising:
 a substrate;   a plurality of electrically conductive traces disposed on at least a portion of the first substrate;   a plurality of barrier layers, each respective barrier layer of the plurality of barrier layers at least partially overlying each respective electrically conductive trace of the plurality of electrically conductive traces;   a plurality of electrically conductive interconnects, each respective electrically conductive interconnect of the plurality of electrically conductive interconnects at least partially overlying each respective barrier layer of the plurality of barrier layers; and   a bonding layer at least partially surrounding the plurality of electrically conductive interconnects,   wherein each respective barrier layer of the plurality of barrier layers is interposed between each respective electrically conductive trace of the plurality of electrically conductive traces and each respective electrically conductive interconnect of the plurality of electrically conductive interconnects; and   wherein each of the plurality of barrier layers is a planar barrier layer.   
     
     
         16 . The electronic device according to  claim 15 ,
 wherein each respective electrically conductive interconnect of the plurality of electrically conductive interconnects extends upright relative to each respective planar barrier layer of the plurality of barrier layers.   
     
     
         17 . The electronic device according to  claim 15 ,
 wherein each respective barrier layer of the plurality of barrier layers extends parallel to each respective electrically conductive trace of the plurality of electrically conductive traces; and   wherein each respective electrically conductive interconnect of the plurality of electrically conductive interconnects extends perpendicularly to each respective barrier layer of the plurality of barrier layers.   
     
     
         18 . An electronic device comprising:
 a substrate;   a plurality of electrically conductive traces disposed on at least a portion of the substrate;   a plurality of barrier layers, each respective barrier layer of the plurality of barrier layers at least partially overlying each respective electrically conductive trace of the plurality of electrically conductive traces;   a plurality of electrically conductive interconnects, each respective electrically conductive interconnect of the plurality of electrically conductive interconnects at least partially overlying each respective barrier layer of the plurality of barrier layers; and   a bonding layer at least partially overlying the plurality of electrically conductive traces and at least partially overlying the plurality of barrier layers, the bonding layer at least partially surrounding the plurality of electrically conductive interconnects;   wherein each respective barrier layer of the plurality of barrier layers underlies at least a portion of the bonding layer, and each respective barrier layer of the plurality of barrier layers is interposed between each respective electrically conductive trace of the plurality of electrically conductive traces and each respective electrically conductive interconnect of the plurality of electrically conductive interconnects; and   wherein each respective barrier layer is configured to prevent interdiffusion between each respective electrically conductive trace and each respective electrically conductive interconnect; and   wherein the bonding layer is made of silicon dioxide.   
     
     
         19 . The electronic device according to  claim 18 ,
 wherein the plurality of electrically conductive traces is a first plurality of electrically conductive traces;   wherein the plurality of barrier layers is a first plurality of barrier layers;   wherein the plurality of electrically conductive interconnects is a first a plurality of electrically conductive interconnects; and   wherein the bonding layer is a first bonding layer;   the electronic device further comprising:
 a second substrate; 
 a second plurality of electrically conductive traces disposed on at least a portion of the second substrate; 
 a second plurality of barrier layers, each respective second barrier layer of the second plurality of barrier layers at least partially overlying each respective second electrically conductive trace of the second plurality of electrically conductive traces; 
 a second plurality of electrically conductive interconnects, each respective second electrically conductive interconnect of the second plurality of electrically conductive interconnects at least partially overlying each respective second barrier layer of the second plurality of barrier layers; and 
 a second bonding layer at least partially overlying the second plurality of electrically conductive traces and at least partially overlying the second plurality of barrier layers, the second bonding layer at least partially surrounding the second plurality of electrically conductive interconnects, 
 wherein each respective second barrier layer of the second plurality of barrier layers is interposed between each respective second electrically conductive trace of the second plurality of electrically conductive traces and each respective second electrically conductive interconnect of the second plurality of electrically conductive interconnects, and 
   wherein the first bonding layer is bonded to the second bonding layer, and   wherein at least one of the first plurality of electrically conductive interconnects is diffusion bonded to at least one of the second plurality of electrically conductive interconnects.   
     
     
         20 . The integrated electronic device according to  claim 19 ,
 wherein at least one of the first plurality of electrically conductive traces and the second plurality of electrically conductive traces are made from aluminum or aluminum alloy;   wherein at least one of the first plurality of electrically conductive interconnects and the second plurality of electrically conductive interconnects are made from nickel or nickel alloy; and   wherein at least one of the first plurality of barrier layers and the second plurality of barrier layers are selected from a group consisting of: titanium nitride, titanium tungsten, tantalum, and tantalum nitride.