Wafer based beol process for chip embedding

Abstract

In various embodiments a semiconductor device is provided, including a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor body having a front side and a back side opposite to the front side, the semiconductor body comprising a semiconductor layer, a first drift region and a first gate electrode arranged laterally adjacent to the first drift region, wherein the first gate electrode vertically extends from the front side of the semiconductor body towards the back side of the semiconductor body, and   a first contact structure provided over the semiconductor body and at least partially horizontally overlapping the first drift region of the semiconductor body, the first contact structure including a first metal layer contacting the semiconductor body at the front side, an adhesion layer disposed over the first metal layer, and a second metal layer disposed over the adhesion layer, wherein the first metal layer of the first contact structure and the first gate electrode do not horizontally overlap.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a second contact structure provided over the semiconductor body and laterally adjacent to the first gate electrode, the second contact structure including a first metal layer contacting the semiconductor body at the front side, an adhesion layer disposed over the first metal layer, and a second metal layer disposed over the adhesion layer, wherein the first metal layer of the second contact structure and the first gate electrode do not horizontally overlap.   
     
     
         3 . The semiconductor device of  claim 2 , further comprising:
 a second drift region of the semiconductor body, wherein the first gate electrode is arranged laterally adjacent to the second drift region; and wherein the second contact structure at least partially horizontally overlaps the second drift region of the semiconductor body.   
     
     
         4 . The semiconductor device of  claim 2 , further comprising:
 a gate portion disposed at the front side of the semiconductor body, wherein the gate portion is electrically coupled to the first gate electrode and is at least partially disposed between the first and second contact structures.   
     
     
         5 . The semiconductor device of  claim 2 , further comprising:
 a third contact structure provided over the semiconductor body, the third contact structure including a first metal layer contacting the semiconductor body at the front side, an adhesion layer disposed over the first metal layer, and a second metal layer disposed over the adhesion layer, wherein the first metal layer of the third contact structure is physically and electrically coupled to gate portion.   
     
     
         6 . The semiconductor device of  claim 5 , wherein top surfaces of the first metal layers of the first, second, and third contact structures are coplanar. 
     
     
         7 . The semiconductor device of  claim 2 , wherein the first metal layers of the first and second contact structures include aluminum. 
     
     
         8 . The semiconductor device of  claim 2 , wherein the adhesion layers of the first and second contact structures include titanium, tantalum, or titanium tungsten. 
     
     
         9 . The semiconductor device of  claim 2 , wherein the second metal layers of the first and second contact structures include copper. 
     
     
         10 . The semiconductor device of  claim 4 , further comprising: dielectric material provided between the first and second contact structures that covers the gate portion. 
     
     
         11 . The semiconductor device of  claim 10 , further comprising: passivation material provided over the dielectric material between the first and second contact structures. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the passivation material is further provided over the first and second contact structures so as to encapsulate the contact structures. 
     
     
         13 . The semiconductor device of  claim 12 , further comprising: an opening provided in the passivation material over the upper surface of each of the first contact structure exposing an upper surface of the first contact structure. 
     
     
         14 . The semiconductor device of  claim 4 , further comprising: a further gate portion provided over the semiconductor body that is electrically coupled to the gate portion, the further gate portion being covered by dielectric material. 
     
     
         15 . The semiconductor device of  claim 2 , wherein the second contact structure is laterally and physically separate from the first contact structure. 
     
     
         16 . The semiconductor device of  claim 2 , wherein upper surfaces of the second metal layer of the first contact structure and of the second metal layer of the second contact structure are level. 
     
     
         17 . The semiconductor device of  claim 4 , wherein upper surfaces of the first metal layer of the first contact structure and of the gate portion are level. 
     
     
         18 . The semiconductor device of  claim 1 , further comprising:
 a back side metal layer provided at the back side of the semiconductor body.   
     
     
         19 . The semiconductor device of  claim 2 , wherein a thickness of the second metal layer of the first and second contact structures is the range from 5 μm to 10 μm. 
     
     
         20 . The semiconductor device of  claim 1 , wherein a thickness of the semiconductor device is in the range from 60 μm to 100 μm.