High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss

Abstract

A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a Group IVA nitride layer in contact with the semiconductor handle substrate, the Group IVA nitride layer selected from the group consisting of carbon nitride, silicon carbon nitride, and a combination thereof; a dielectric layer in contact with the Group IVA nitride layer; and a semiconductor device layer in contact with the dielectric layer.

What is claimed is: 
     
         1 . A multilayer structure comprising:
 a silicon wafer handle substrate comprising two major, generally parallel surfaces, one of which is a front surface of the silicon wafer handle substrate and the other of which is a back surface of the silicon wafer handle substrate, a circumferential edge joining the front and back surfaces of the silicon wafer handle substrate, and a bulk region between the front and back surfaces of the silicon wafer handle substrate, wherein the silicon wafer handle substrate has a bulk region resistivity between 2000 Ohm-cm and about 100,000 Ohm-cm;   a charge trapping layer comprising a Group IVA nitride layer, wherein the Group IVA nitride layer comprises silicon carbon nitride;   a dielectric layer in contact with the Group IVA nitride layer, wherein the dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, and a combination thereof; and   a semiconductor device layer in contact with the dielectric layer.   
     
     
         2 . The multilayer structure of  claim 1  wherein the silicon wafer handle substrate has a bulk resistivity between about 2000 Ohm-cm and about 10,000 Ohm-cm. 
     
     
         3 . The multilayer structure of  claim 1  wherein the silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 10,000 Ohm-cm. 
     
     
         4 . The multilayer structure of  claim 1  wherein the silicon wafer handle substrate has a bulk resistivity between about 3000 Ohm-cm and about 5,000 Ohm-cm. 
     
     
         5 . The multilayer structure of  claim 1  wherein the charge trapping layer is in interfacial contact with an oxide free front surface of the silicon wafer handle substrate. 
     
     
         6 . The multilayer structure of  claim 1  wherein the charge trapping layer comprising the Group IVA nitride layer comprises crystalline silicon carbon nitride. 
     
     
         7 . The multilayer structure of  claim 1  wherein the charge trapping layer comprising the Group IVA nitride layer comprises amorphous silicon carbon nitride. 
     
     
         8 . The multilayer structure of  claim 1  wherein the charge trapping layer comprising the Group IVA nitride layer has an average thickness of between about 1 nanometer and about 2000 nanometers. 
     
     
         9 . The multilayer structure of  claim 1  wherein the charge trapping layer comprising the Group IVA nitride layer has an average thickness of between about 5 nanometers and about 2000 nanometers. 
     
     
         10 . The multilayer structure of  claim 1  wherein the charge trapping layer comprising the Group IVA nitride layer has an average thickness of between about 5 nanometers and about 1000 nanometers. 
     
     
         11 . The multilayer structure of  claim 1  wherein the charge trapping layer comprising the Group IVA nitride layer has an average thickness of between about 5 nanometers and about 500 nanometers. 
     
     
         12 . The multilayer structure of  claim 1  wherein the charge trapping layer comprising the Group IVA nitride layer has an average thickness of between about 200 nanometers and about 500 nanometers.