US2019252497A1PendingUtilityA1

Long channels for transistors

Assignee: IBMPriority: Dec 18, 2017Filed: Apr 23, 2019Published: Aug 15, 2019
Est. expiryDec 18, 2037(~11.4 yrs left)· nominal 20-yr term from priority
H10P 50/642H10D 64/0116H01L 21/823431H01L 29/7827H01L 29/66446H01L 29/1037H01L 29/66666H01L 29/66795H01L 21/28575H01L 29/6656H01L 21/30604H01L 29/7851H01L 29/66545H10D 84/834H10D 84/0158H10D 84/038H10D 64/021H10D 64/017H10D 30/6211H10D 30/63H10D 30/025H10D 30/024H10D 30/01H10D 62/292
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Claims

Abstract

A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first fin, a second fin, and a third fin arranged on a substrate;   a gate arranged on the first fin, the second fin, and the third fin;   a channel extending through the gate and from the first fin, the second fin, and to the third fin in a serpentine fashion; and   a first source/drain and a second source/drain arranged on opposing sides of the gate.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the channel extends through the gate in three areas. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the first fin and the second fin are coupled on one side of the gate. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the second fin and the third fin are coupled on another side of the gate. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the first fin and the second fin are coupled by overlapping epitaxial growth. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the second fin and the third fin are coupled by overlapping epitaxial growth. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first fin and the second fin are coupled by a metal-filled trench. 
     
     
         8 . The semiconductor device of  claim 7 , wherein and the second fin and the third fin are coupled by a metal-filled trench. 
     
     
         9 . The semiconductor device of  claim 1 , wherein the first fin, the second fin, and the third fin each comprise an epitaxial growth. 
     
     
         10 . A semiconductor device, comprising:
 a first fin, a second fin, and a third fin arranged on a substrate;   a gate arranged on the first fin, the second fin, and the third fin;   a channel extending through the gate and from the first fin, the second fin, and to the third fin in a serpentine fashion, the channel comprising a length greater than 100 nanometers (nm); and   a first source/drain and a second source/drain arranged on opposing sides of the gate.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the channel extends through the gate in three areas. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the first fin and the second fin are coupled on one side of the gate. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the second fin and the third fin are coupled on another side of the gate. 
     
     
         14 . The semiconductor device of  claim 12 , wherein the first fin and the second fin are coupled by overlapping epitaxial growth. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the second fin and the third fin are coupled by overlapping epitaxial growth. 
     
     
         16 . The semiconductor device of  claim 10 , wherein the first fin and the second fin are coupled by a metal-filled trench. 
     
     
         17 . The semiconductor device of  claim 16 , wherein and the second fin and the third fin are coupled by a metal-filled trench. 
     
     
         18 . The semiconductor device of  claim 10 , wherein the first fin, the second fin, and the third fin each comprise an epitaxial growth. 
     
     
         19 . A semiconductor device, comprising:
 a first fin, a second fin, and a third fin arranged on a substrate; and   a channel extending through the gate and from the first fin, the second fin, and to the third fin in a serpentine fashion.   
     
     
         20 . The semiconductor device of  claim 19 , wherein the channel extends through the gate in three areas.

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