Multiple-threshold nanosheet transistors

Abstract

Semiconductor devices and methods of making the same include forming a stack of alternating layers of channel material and sacrificial material. The sacrificial material is etched away to free the layers of channel material. A gate stack is formed around the layers of channel material. At least one layer of channel material is deactivated. Source and drain regions are formed in contact with the at least one layer of active channel material.

1 . A method of forming a semiconductor device, comprising:
 forming a stack of alternating layers of channel material and sacrificial material;   etching away the sacrificial material to free the layers of channel material;   forming a gate stack around the layers of channel material;   deactivating at least one layer of channel material; and   forming source and drain regions in contact with the at least one layer of active channel material.   
     
     
         2 . The method of  claim 1 , wherein deactivating the at least one layer of channel material comprises etching away at least one of the topmost layers of channel material. 
     
     
         3 . The method of  claim 2 , wherein deactivating the at least one layer of channel material further comprises forming a dielectric layer that covers exposed surfaces of at least one of the bottommost layers of channel material prior to forming the source and drain regions. 
     
     
         4 . The method of  claim 1 , wherein deactivating the at least one layer of channel material comprises doping a top layer of channel material to raise a threshold voltage for the doped layer above an operating voltage. 
     
     
         5 . The method of  claim 4 , wherein deactivating the at least one layer of channel material further comprises forming a dielectric layer that covers exposed surfaces of at least one of the bottommost layers of channel material prior to forming the source and drain regions. 
     
     
         6 . The method of  claim 4 , wherein deactivating the at least one layer of channel material comprises doping the top layer of channel material with a dopant concentration of at least 1×10 19 /cm 3 . 
     
     
         7 . The method of  claim 4 , wherein doping the top layer of channel material comprises a low-energy implantation process that only implants dopants as far as the top layer of channel material. 
     
     
         8 . The method of  claim 7 , wherein doping the top layer of channel material comprises doping with a p-type dopant at an implantation energy between 10 KeV and 20 KeV. 
     
     
         9 . The method of  claim 7 , wherein doping the top layer of channel material comprises doping with an n-type dopant at an implantation energy between 5 KeV and 10 KeV. 
     
     
         10 . The method of  claim 1 , wherein deactivating the at least one layer of channel material comprises forming a dielectric layer that covers exposed surfaces of every layer of channel material except for a top layer of channel material prior to forming the source and drain regions. 
     
     
         11 . The method of  claim 10 , wherein each layer of channel material has a different associated voltage threshold based on dimensions and composition of the respective layer. 
     
     
         12 . A semiconductor device, comprising:
 a plurality of vertically aligned layers of channel material, wherein all but one of the plurality of layers of channel material are deactivated, leaving one activated layer of channel material;   a gate stack formed around the plurality of layers of channel material; and   a source and drain region in contact with respective ends of the one activated layer of channel material.   
     
     
         13 . The semiconductor device of  claim 12 , further comprising a dielectric layer that covers ends of the deactivated layers of channel material, wherein the source and drain region are formed above the dielectric layer. 
     
     
         14 . The semiconductor device of  claim 12 , wherein a top layer of channel material is doped to have a threshold voltage above an operating voltage. 
     
     
         15 . The semiconductor device of  claim 14 , wherein the doped top layer of channel material has a dopant concentration of at least 1×10 19 /cm 3 . 
     
     
         16 . The semiconductor device of  claim 12 , wherein each of the plurality of layers of channel material has a different associated threshold voltage based on dimensions and composition of the respective layer. 
     
     
         17 . An integrated circuit, comprising:
 a plurality of field effect transistors (FETs), each FET having a different respective threshold voltage in accordance with an activated channel layer, each FET comprising:
 a plurality of vertically aligned layers of channel material, each of the plurality of layers having a different associated threshold voltage, wherein all but one of the plurality of layers of channel material are deactivated, leaving one activated layer of channel material; 
 a gate stack formed around the plurality of layers of channel material; and 
 a source and drain region in contact with respective ends of the one activated layer of channel material. 
   
     
     
         18 . The integrated circuit of  claim 17 , wherein at least one FET further comprises a dielectric layer that covers ends of the FET's respective deactivated layers of channel material, wherein the FET's respective source and drain region are formed above the dielectric layer. 
     
     
         19 . The integrated circuit of  claim 17 , wherein a top layer of channel material of at least one FET is doped to have a threshold voltage above an operating voltage. 
     
     
         20 . The integrated circuit of  claim 19 , wherein the doped top layer of channel material has a dopant concentration of at least 1×10 19 /cm 3 .