Semiconductor device having data storage pattern

Abstract

A semiconductor device including a data storage pattern is provided. The semiconductor device includes a first conductive line disposed on a substrate and extending in a first direction, a second conductive line disposed on the first conductive line and extending in a second direction, and a first data storage structure and a first selector structure disposed between the first conductive line and the second conductive line and connected in series. The first data storage structure includes a first lower data storage electrode, a first data storage pattern, and a first upper data storage electrode. The first lower data storage electrode includes a first portion facing the first upper data storage electrode and vertically aligned with the first upper data storage electrode. The first data storage pattern includes a first side surface and a second side surface facing each other. The first upper data storage electrode and the first portion of the first lower data storage electrode are disposed to be closer to the first side surface of the first data storage pattern than to the second side surface of the first data storage pattern.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a selector structure; and   a data storage structure on the selector structure,   wherein the selector structure includes a first selector electrode, a selector pattern on the first selector electrode, and a second selector electrode on the selector pattern,   wherein the data storage structure includes a first conductive pattern, a data storage pattern on the first conductive pattern, and a second conductive pattern on the data storage pattern,   wherein a width of at least a portion of the data storage pattern is smaller than a width of the selector pattern,   wherein at least one sidewall of the second conductive pattern is self-aligned with at least one sidewall of the data storage pattern,   wherein a width of at least a portion of the second conductive pattern is smaller than a width of the selector pattern, and   wherein a width of at least a portion of the first conductive pattern is greater than a width of at least a portion of the second conductive pattern.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the data storage pattern is in contact with the first conductive pattern and the second conductive pattern. 
     
     
         3 . The semiconductor device of  claim 1 , wherein a sidewall of the selector pattern is self-aligned with a sidewall of the first selector electrode and a sidewall of the second selector electrode. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the selector pattern is in contact with the first selector electrode and the second selector electrode. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the data storage pattern includes a phase change material. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the selector pattern includes a chalcogenide-based material different from the phase change material of the data storage pattern. 
     
     
         7 . A semiconductor device, comprising:
 a first conductive line;   a second conductive line disposed on the first conductive line;   a selector structure disposed between the first conductive line and the second conductive line; and   a data storage structure disposed between the first conductive line and the second conductive line,   wherein the selector structure includes a first selector electrode, a selector pattern on the first selector electrode, and a second selector electrode on the selector pattern,   wherein the data storage structure includes a first conductive pattern, a data storage pattern on the first conductive pattern, and a second conductive pattern on the data storage pattern,   wherein a width of at least a portion of the data storage pattern is smaller than a width of the selector pattern,   wherein at least one sidewall of the second conductive pattern is self-aligned with at least one sidewall of the data storage pattern,   wherein a width of at least a portion of the second conductive pattern is smaller than a width of the selector pattern, and   wherein a width of at least a portion of the first conductive pattern is greater than a width of at least a portion of the second conductive pattern.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the data storage pattern is in contact with the first conductive pattern and the second conductive pattern. 
     
     
         9 . The semiconductor device of  claim 7 , wherein a sidewall of the selector pattern is self-aligned with a sidewall of the first selector electrode and a sidewall of the second selector electrode. 
     
     
         10 . The semiconductor device of  claim 7 , wherein the selector pattern is in contact with the first selector electrode and the second selector electrode. 
     
     
         11 . The semiconductor device of  claim 7 , wherein the data storage pattern includes a phase change material. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the selector pattern includes a chalcogenide-based material different from the phase change material. 
     
     
         13 . The semiconductor device of  claim 11 , wherein the first conductive pattern is disposed between the data storage pattern and the second selector electrode. 
     
     
         14 . The semiconductor device of  claim 11 , wherein the second conductive pattern is disposed between the data storage pattern and the first selector electrode. 
     
     
         15 . A semiconductor device, comprising:
 a first conductive line;   a second conductive line disposed on the first conductive line;   a third conductive line disposed on the second conductive line;   a lower selector structure disposed between the first conductive line and the second conductive line;   a lower data storage structure disposed between the first conductive line and the second conductive line;   an upper selector structure disposed between the second conductive line and the third conductive line; and   an upper data storage structure disposed between the second conductive line and the third conductive line,   wherein the lower selector structure includes a first lower selector electrode, a lower selector pattern on the first lower selector electrode, and a second lower selector electrode on the lower selector pattern,   wherein the lower data storage structure includes a first lower conductive pattern, a lower data storage pattern on the first lower conductive pattern, and a second lower conductive pattern on the lower data storage pattern,   wherein a width of at least a portion of the lower data storage pattern is smaller than a width of the lower selector pattern,   wherein at least one sidewall of the second lower conductive pattern is self-aligned with at least one sidewall of the lower data storage pattern,   wherein a width of at least a portion of the second lower conductive pattern is smaller than a width of the lower selector pattern, and   wherein a width of at least a portion of the first lower conductive pattern is greater than a width of at least a portion of the second lower conductive pattern.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the lower data storage pattern is in contact with the first lower conductive pattern and the lower second conductive pattern, and
 wherein the lower selector pattern is in contact with the first lower selector electrode and the second lower selector electrode.   
     
     
         17 . The semiconductor device of  claim 15 , wherein a sidewall of the lower selector pattern is self-aligned with a sidewall of the first lower selector electrode and a sidewall of the second lower selector electrode. 
     
     
         18 . The semiconductor device of  claim 15 ,
 wherein the upper selector structure includes a first upper selector electrode, a upper selector pattern on the first upper selector electrode, and a second upper selector electrode on the upper selector pattern,   wherein the upper data storage structure includes a first upper conductive pattern, a upper data storage pattern on the first upper conductive pattern, and a second upper conductive pattern on the upper data storage pattern,   wherein a width of at least a portion of the upper data storage pattern is smaller than a width of the upper selector pattern,   wherein at least one sidewall of the second upper conductive pattern is self-aligned with at least one sidewall of the upper data storage pattern,   wherein a width of at least a portion of the second upper conductive pattern is smaller than a width of the upper selector pattern, and   wherein a width of at least a portion of the first upper conductive pattern is greater than a width of at least a portion of the second upper conductive pattern.   
     
     
         19 . The semiconductor device of  claim 18 , wherein the upper data storage pattern is in contact with the first upper conductive pattern and the upper second conductive pattern, and
 wherein the upper selector pattern is in contact with the first upper selector electrode and the second upper selector electrode.   
     
     
         20 . The semiconductor device of  claim 18 , wherein a sidewall of the upper selector pattern is self-aligned with a sidewall of the first upper selector electrode and a sidewall of the second upper selector electrode.