Chip Warpage Reduction Via Raised Free Bending & Re-entrant (Auxetic) Trace Geometries

Abstract

A microelectronic device and method of making the same including a substrate and at least one expansion layer that adds stress to the substrate when said substrate expands.

What is claimed is: 
     
         1 . A microelectronic device comprising: a substrate; at least one expansion layer connected to said substrate; and wherein when said substrate expands said at least one expansion layer becomes thicker perpendicular to the direction of expansion. 
     
     
         2 . The microelectronic device of  claim 1  wherein said at least one expansion layer includes at least one pattern comprised of an auxetic shape. 
     
     
         3 . The microelectronic device of  claim 1  wherein said at least one expansion layer includes at least one pattern comprised of a curved shape. 
     
     
         4 . The microelectronic device of  claim 1  wherein said at least one expansion layer includes at least one pattern comprised of a closed curved shape. 
     
     
         5 . The microelectronic device of  claim 1  wherein said at least one expansion layer has a coefficient of expansion greater than said substrate and said at least one expansion layer adds stress to said substrate when said substrate expands. 
     
     
         6 . A microelectronic device comprising: a substrate, at least one expansion layer located a spaced distance above and apart from said substrate; one or more connectors located between said substrate and said at least one expansion layer, said one or more connectors connected to said substrate and said at least one expansion layer; wherein when said substrate expands said at least one expansion layer becomes thicker perpendicular to the direction of expansion. 
     
     
         7 . The microelectronic device of  claim 6  wherein said at least one expansion layer includes at least one pattern comprised of an auxetic shape. 
     
     
         8 . The microelectronic device of  claim 6  wherein said at least one expansion layer includes at least one pattern comprised of a curved shape. 
     
     
         9 . The microelectronic device of  claim 6  wherein said at least one expansion layer includes at least one pattern comprised of a closed curved shape. 
     
     
         10 . The microelectronic device of  claim 6  wherein said at least one expansion layer has a coefficient of expansion greater than said substrate and said at least one expansion layer adds stress to said substrate when said substrate expands. 
     
     
         11 . The microelectronic device of  claim 6  wherein when said substrate expands said at least one expansion layer has a greater expansion such that said expansion of said expansion layer is mitigated within said expansion layer, rather than at the interface of said substrate. 
     
     
         12 . A method of reducing the warpage of a substrate in a microelectronic comprising the steps of: forming at least one expansion layer on said substrate wherein when said substrate expands said at least one expansion layer becomes thicker perpendicular to the direction of expansion. 
     
     
         13 . The method of  claim 12  wherein said at least one expansion layer includes at least one pattern comprised of an auxetic shape. 
     
     
         14 . The method of  claim 12  wherein said at least one expansion layer includes at least one pattern comprised of a curved shape. 
     
     
         15 . The method of  claim 12  wherein said at least one expansion layer includes at least one pattern comprised of a closed curved shape. 
     
     
         16 . The method of  claim 12  wherein said at least one expansion layer has a coefficient of expansion greater than said substrate and said at least one expansion layer adds stress to said substrate when said substrate expands. 
     
     
         17 . A method of reducing the warpage of a substrate in a microelectronic comprising the steps of: forming a layer comprised of one or more connectors on the substrate; forming at least one expansion layer on said connector layer to locate said at least one expansion layer a spaced distance above and apart from said substrate; wherein when said substrate expands said at least one expansion layer becomes thicker perpendicular to the direction of expansion. 
     
     
         18 . The method of  claim 17  wherein said at least one expansion layer includes at least one pattern comprised of an auxetic shape. 
     
     
         19 . The method of  claim 17  wherein said at least one expansion layer includes at least one pattern comprised of a curved shape. 
     
     
         20 . The method of  claim 17  wherein said at least one expansion layer includes at least one pattern comprised of a closed curved shape. 
     
     
         21 . The method of  claim 17  wherein said at least one expansion layer has a coefficient of expansion greater than said substrate and said at least one expansion layer adds stress to said substrate when said substrate expands.