Frequent Data Value Compression for Graphics Processing Units

Abstract

A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline from memory, first the control surface bits are read. If they happen to be set, then the original memory read is skipped altogether and instead the bits from the control surface provide the value for the entire cacheline.

What is claimed: 
     
         1 . A method comprising:
 providing a first unique code to indicate at least one common data pattern for an entire cacheline, where a common data pattern is made up of repeating identical single data values;   providing a second unique code to indicate at least one repeating data pattern for less than an entire cacheline, where a repeating data pattern is made up of a sequence of more than one data value, said sequence repeating within less than an entire cacheline;   in response to detecting a common data pattern, writing a first unique code, instead of writing the common data pattern;   upon identifying said first unique code during a cacheline read, substituting for the first unique code, the common data pattern represented by the first unique code;   in response to detecting a repeating data pattern, writing a second unique code, instead of writing the common data pattern, wherein the first and second unique codes are different codes; and   upon identifying the second unique code during a cacheline read, substituting for the second unique code, the repeating data pattern represented by the second unique code.   
     
     
         2 . The method of  claim 1  wherein the common data pattern is repeated zeros or repeated ones. 
     
     
         3 . The method of  claim 1  providing a first or second unique code only if a cacheline is entirely composed of a single common data pattern or a single repeating data pattern. 
     
     
         4 . The method of  claim 1  including encoding the first unique code and the second unique code each including only two bits. 
     
     
         5 . The method of  claim 4  including using one of the two bits to indicate that whether the code represents a common data pattern or a repeating data pattern. 
     
     
         6 . The method of  claim 1  including using preprogrammed common and repeating data patterns and corresponding codes. 
     
     
         7 . The method of  claim 1  including identifying a common or repeating data pattern during compile time. 
     
     
         8 . The method of  claim 1  including identifying a common or repeating data pattern during run time. 
     
     
         9 . The method of  claim 1  including monitoring streams for a plurality of common data patterns or a plurality of repeating data patterns, each of said pluralities of patterns represented by a different first or second unique code. 
     
     
         10 . The method of  claim 1  including detecting the repeating data pattern, and generating control information to specify a width of the repeating pattern, a number of patterns and lanes that will carry the repeating data patterns. 
     
     
         11 . One or more non-transitory computer readable media storing instructions to perform a sequence comprising:
 providing a first unique code to indicate at least one common data pattern for an entire cacheline, where a common data pattern is made up of repeating identical single data values;   providing a second unique code to indicate at least one repeating data pattern for less than an entire cacheline, where a repeating data pattern is made up of a sequence of more than one data value, said sequence repeating within less than an entire cacheline;   in response to detecting a common data pattern, writing a first unique code, instead of writing the common data pattern;   upon identifying said first unique code during a cacheline read, substituting for the first unique code, the common data pattern represented by the first unique code;   in response to detecting a repeating data pattern, writing a second unique code, instead of writing the common data pattern, wherein the first and second unique codes are different codes; and   upon identifying the second unique code during a cacheline read, substituting for the second unique code, the repeating data pattern represented by the second unique code.   
     
     
         12 . The media of  claim 11 , further storing instructions to perform a sequence wherein the common data platform is repeated zeros or repeated ones. 
     
     
         13 . The media of  claim 11 , further storing instructions to perform a sequence providing a first or second unique code only if a cacheline is entirely composed of a single common data pattern or a single repeating data pattern. 
     
     
         14 . The media of  claim 11 , further storing instructions to perform a sequence including encoding the first unique code and the second unique code each including only two bits. 
     
     
         15 . The media of  claim 14 , further storing instructions to perform a sequence including using one of the two bits to indicate that whether the code represents a common data pattern or a repeating data pattern. 
     
     
         16 . The media of  claim 11 , further storing instructions to perform a sequence including using preprogrammed common and repeating data patterns and corresponding codes. 
     
     
         17 . The media of  claim 11 , further storing instructions to perform a sequence including identifying a common or repeating data pattern during compile time. 
     
     
         18 . The media of  claim 11 , further storing instructions to perform a sequence including identifying a common or repeating data pattern during run time. 
     
     
         19 . The media of  claim 11 , further storing instructions to perform a sequence including monitoring streams for a plurality of common data patterns or a plurality of repeating data patterns, each of said pluralities of patterns represented by a different first or second unique code. 
     
     
         20 . The media of  claim 11 , further storing instructions to perform a sequence including detecting the repeating data pattern, and generating control information to specify a width of the repeating data pattern, a number of patterns and lanes that will carry the repeating patterns. 
     
     
         21 . An apparatus comprising:
 a processor to provide a first unique code to indicate at least one common data pattern for an entire cacheline, where a common data pattern is made up of repeating identical single data values, provide a second unique code to indicate at least one repeating data pattern for less than an entire cacheline, where a repeating data pattern is made up of a sequence of more than one data value, said sequence repeating within less than an entire cacheline, in response to detecting a common data pattern, writing a first unique code, instead of writing the common data pattern, upon identifying said first unique code during a cacheline read, substitute for the first unique code, the common data pattern represented by the first unique code, in response to detecting a repeating data pattern, write a second unique code, instead of writing the common data pattern, wherein the first and second unique codes are different codes, upon identifying the second unique code during a cacheline read, substitute for the second unique code, the repeating data pattern represented by the second unique code; and   a memory coupled to said processor.   
     
     
         22 . The apparatus of  claim 21  wherein the common data pattern is repeated zeros or repeated ones. 
     
     
         23 . The apparatus of  claim 21  wherein providing a first or second unique code only if a cacheline is entirely composed of a single common data pattern or a single repeating data pattern. 
     
     
         24 . The apparatus of  claim 21 , said processor to encode the first unique code and the second unique code each including only two bits. 
     
     
         25 . The apparatus of  claim 24 , said processor to use one of the two bits to indicate that whether the code represents a common data pattern or a repeating data pattern. 
     
     
         26 . The apparatus of  claim 21 , said processor to use preprogrammed common and repeating data patterns and corresponding codes. 
     
     
         27 . The apparatus of  claim 21 , said processor to identify a common or repeating data pattern during compile time. 
     
     
         28 . The apparatus of  claim 21 , said processor to identify a common or repeating data pattern during run time. 
     
     
         29 . The apparatus of  claim 21 , said processor to monitor streams for a plurality of common data patterns or a plurality of repeating data patterns, each of said pluralities of patterns represented by a different first or second unique code. 
     
     
         30 . The apparatus of  claim 21 , said processor to detect the repeating data pattern, and generate control information to specify a width of the repeating data pattern, a number of patterns and lanes that will carry the repeating data patterns. 
     
     
         31 . The apparatus of  claim 21 , including a transmitter to receive parallel input data and to transmit a plurality of serial streams of encoded output data. 
     
     
         32 . The method of  claim 1  including adding the code to a tag for a cacheline.