Silicon-based optical ports providing passive alignment connectivity

Abstract

Optical ports providing passive alignment connectivity are disclosed. In one embodiment, an optical port includes a substrate having a surface, a photonic silicon chip, a connector body, and a plurality of spacer elements. The photonic silicon chip includes an electrical coupling surface, an upper surface and an optical coupling surface. The optical coupling surface is positioned between the electrical coupling surface and the upper surface. The photonic silicon chip further includes at least one waveguide terminating at the optical coupling surface, and a chip engagement feature disposed on the upper surface. The connector body includes a first alignment feature, a second alignment feature, a mounting surface, and a connector engagement feature at the mounting surface. The connector engagement feature mates with the chip engagement feature. The plurality of spacer elements is disposed between the electrical coupling surface of the photonic silicon chip and the surface of the substrate.

What is claimed is: 
     
         1 . An optical port comprising:
 a substrate comprising a surface;   a photonic silicon chip secured to the substrate, the photonic silicon chip comprising:
 an electrical coupling surface, an upper surface and an optical coupling surface, wherein the optical coupling surface is positioned between the electrical coupling surface and the upper surface; and 
 at least one optical waveguide terminating at the optical coupling surface; 
   a wafer disposed on the upper surface of the photonic silicon chip, the wafer comprising:
 an upper surface; 
 a groove within the upper surface; and 
 a first bore and a second bore within the upper surface, wherein the first bore and the second bore are on opposite sides of the groove and proximate the mechanical coupling surface; 
   an alignment cylinder disposed within the groove of the wafer; and   a connector body secured to the substrate, the connector body comprising:
 a mounting surface; 
 a first alignment feature and a second alignment feature; and 
 a groove within the mechanical coupling surface, and a first alignment peg and a second alignment peg extending from the mounting surface on opposite sides of the groove, wherein:
 the photonic silicon chip is disposed within a recess defined by the mounting surface of the connector body and the surface of the substrate; 
 the first alignment peg and the second alignment peg are disposed within the first bore and the second bore of the wafer, respectively; and 
 the alignment cylinder is disposed within the groove of the connector body. 
 
   
     
     
         2 . The optical port of  claim 1 , wherein:
 the wafer comprises a third bore; and   the connector body comprises a third alignment peg extending from the mounting surface; and   the third alignment peg of the connector body is disposed within the third bore of the wafer.   
     
     
         3 . The optical port of  claim 1 , wherein:
 the substrate comprises a first trench and a second trench within the surface;   the connector body comprises a first leg portion and a second leg portion;   the first leg portion is disposed in the first trench;   the second leg portion is disposed within the second trench; and   the first leg portion and the second leg portion are secured to the substrate within the first trench and the second trench, respectively, by an adhesive.   
     
     
         4 . The optical port of  claim 3 , wherein the connector body further comprises a notch positioned between the first leg portion and the second leg portion. 
     
     
         5 . The optical port of  claim 3 , wherein:
 the connector body further comprises a mechanical coupling surface intersecting the mounting surface;   the first alignment feature is configured as a first alignment bore at the mechanical coupling surface; and   the second alignment feature is configured as a second alignment bore at the mechanical coupling surface.   
     
     
         6 . The optical port of  claim 1 , wherein the photonic silicon chip is electrically coupled to the substrate by a ball grid array. 
     
     
         7 . The optical port of  claim 1 , wherein the photonic silicon chip comprises at least one optical source optically coupled to the at least one optical waveguide. 
     
     
         8 . The optical port of  claim 1 , further comprising a circuit board, wherein the substrate is electrically coupled to the circuit board by a ball grid array. 
     
     
         9 . An optical port comprising:
 a substrate comprising a surface and a plurality of grooves within the surface;   a photonic silicon chip secured to the substrate, the photonic silicon chip comprising:
 an electrical coupling surface, an upper surface and an optical coupling surface, wherein the optical coupling surface is positioned between the electrical coupling surface and the upper surface, and the electrical coupling surface contacts the surface of the substrate; 
 at least one optical waveguide terminating at the optical coupling surface; and 
 a chip engagement feature disposed on the upper surface; 
   a plurality of electrically conductive elements within the plurality of grooves within the surface, wherein the plurality of electrically conductive elements electrically couples the photonic silicon chip to the substrate; and   a connector body secured to the substrate, the connector body comprising:
 a mounting surface, wherein the photonic silicon chip is disposed within a recess defined by the mounting surface of the connector body and the surface of the substrate; 
 a connector engagement feature at the mounting surface, wherein the connector engagement feature mates with the chip engagement feature of the photonic silicon chip; and 
 a first alignment feature and a second alignment feature. 
   
     
     
         10 . The optical port of  claim 9 , wherein:
 the substrate comprises a first trench and a second trench within the surface;   the connector body comprises a first leg portion and a second leg portion;   the first leg portion is disposed in the first trench;   the second leg portion is disposed within the second trench; and   the first leg portion and the second leg portion are secured to the substrate within the first trench and the second trench, respectively, by an adhesive.   
     
     
         11 . The optical port of  claim 10 , wherein the connector body further comprises a notch positioned between the first leg portion and the second leg portion. 
     
     
         12 . The optical port of  claim 10 , wherein:
 the connector body further comprises a mechanical coupling surface intersecting the mounting surface;   the first alignment feature is configured as a first alignment bore at the mechanical coupling surface; and   the second alignment feature is configured as a second alignment bore at the mechanical coupling surface.   
     
     
         13 . The optical port of  claim 9 , wherein:
 the chip engagement feature is a groove within the upper surface of the photonic silicon chip;   the connector engagement feature is a rib portion at the mounting surface; and   the rib portion of the connector body is disposed within the groove of the photonic silicon chip.   
     
     
         14 . The optical port of  claim 9 , wherein the photonic silicon chip comprises at least one optical source optically coupled to the at least one optical waveguide. 
     
     
         15 . The optical port of  claim 9 , wherein the plurality of electrically conductive elements is configured as a ball grid array.