System and methods for dynamic pixel management of a cross pixel interconnected cmos image sensor

Abstract

A camera using a CMOS image sensor based on a shared pixel array technology avails both high definition (HD) and ultra-high definition (UHD) resolution mode formats. Dynamic pixel management allows for both sequential and binned timing formats of pixel signals using switched capacitor noise reduction techniques. When UHD resolution mode is selected, noise can be reduced using both digital double sampling (DDS) or differential digital double sampling (dDDS), and when HD resolution mode is selected noise can be reduced using DDS. Additionally, both rolling shutter and global shutter modes can be selected when HD resolution mode is selected.

What is claimed is: 
     
         1 . A n  image sensor, comprising:
 a plurality of rows of pixels that each include at least one pixel having a plurality of photodiodes and a common readout circuit configured to store respective output voltages from each of the plurality of photodiodes; and   an image sensor controller configured to concurrently control the at least one pixel in at least two rows of the plurality of rows of pixels, such that respective output voltage of at least one photodiode in each of the at least two rows of pixels is concurrently read out on at least one readout channel coupled to the respective common readout circuits,   wherein the at least two rows of pixels comprise a linear configuration and have a symmetrical layout that is identical to each other.   
     
     
         2 . The image sensor according to  claim 1 , wherein the at least one pixel of each row of pixels comprises a plurality of transfer gates that are each coupled to a corresponding photodiode of the plurality of photodiodes. 
     
     
         3 . The image sensor according to  claim 2 , wherein the common readout circuit is further configured to output the stored output voltage of each of the plurality of photodiodes to the at least one readout channel. 
     
     
         4 . The image sensor according to  claim 2 , wherein the image sensor controller is further configured to sequentially activate each transfer gate of the plurality of transfer gates of the at least two rows of pixels to sequentially output respective output voltage of each of the plurality of photodiodes in the respective pixel. 
     
     
         5 . The image sensor according to  claim 4 , wherein the image sensor controller is further configured to concurrently activate each corresponding transfer gate of the plurality of transfer gates in the at least two rows of pixels, such that the output voltages from the respective photodiodes is concurrently read out on the at least one readout channel as the image sensor controller sequentially activates the respective transfer gates in the at least two rows of pixels. 
     
     
         6 . The image sensor of  claim 2 , wherein a first photodiode of the plurality of photodiodes in the at least one pixel in a first row of the at least two rows of pixels is associated with a first transfer gate of the plurality of transfer gates in the first row, and a first photodiode of the plurality of photodiodes in the at least one pixel in a second row of the at least two rows of pixels is associated with a first transfer gate of the plurality of transfer gates in the second row. 
     
     
         7 . The image sensor of  claim 6 , wherein the first photodiode in the at least one pixel in the first row and the first photodiode in the at least one pixel in the second row are on different columns. 
     
     
         8 . The image sensor of  claim 7 , wherein a second transfer gate of the first plurality of transfer gates is coupled to a second transfer gate of the second plurality of transfer gates. 
     
     
         9 . The image sensor of  claim 8 , further comprising:
 a third row of pixels comprising a third pixel that includes:
 a plurality of photodiodes, 
 a plurality of transfer gates coupled to the plurality of photodiodes of the third row of pixels, and 
 a common readout circuit that includes a common storage node physically positioned between each of the plurality of photodiodes and the at least one readout channel and that is configured to store an output voltage from each of the plurality of photodiodes of the third row of pixels and output the stored output voltage to the at least one readout channel. 
   
     
     
         10 . The image sensor of  claim 9 , wherein one of the at least two rows of pixels is directly adjacent to the third row of pixels. 
     
     
         11 . The image sensor of  claim 2 , wherein a connection for coupling respective transfer gates of the at least two rows of pixels is at an edge of an image area including the at least two rows of pixels. 
     
     
         12 . The image sensor of  claim 1 , wherein the at least two rows of pixels are directly adjacent to each other in a horizontal layout of the image sensor. 
     
     
         13 . The image sensor of  claim 1 , further comprising a first operational mode controller configured to control the image sensor in a first operational mode to concurrently sample output values of respective plurality of photodiodes in at least one row of the at least two rows of pixels. 
     
     
         14 . The image sensor according to  claim 13 , wherein the first operational mode is a high definition (HD) mode and a second operational mode is an ultra-high definition (UHD) mode. 
     
     
         15 . The image sensor according to  claim 14 , further comprising an image generating unit configured to generate image data based on at least one of the individually sampled photodiodes during the UHD mode and the collectively sampled photodiodes during the HD mode. 
     
     
         16 . The image sensor according to  claim 15 , further comprising a second operation mode controller configured to control the image sensor to sequentially transfer charge between at least two photodiodes of the plurality of photodiodes of the at least one row of the at least two rows of pixels and the respective common readout circuit 
     
     
         17 . The image sensor according to  claim 16 , wherein the second operation mode controller is further configured to control the image sensor to sample photodiode outputs according to a rolling shutter exposure sequence during the UHD mode. 
     
     
         18 . A n  image sensor controller for controlling a pixel array having a plurality of rows of pixels that each have a plurality of photodiodes and a common readout circuit, the image sensor controller comprising:
 an image sensor controlling means for concurrently controlling at least one pixel in at least two rows of the plurality of rows of pixels to concurrently generate respective output voltages from at least one photodiode in each of the at least two rows of pixels, with the at least two rows of pixels having a linear configuration and a symmetrical layout that is identical to each other; and   a readout controlling means for controlling the at least one pixel in the at least two rows of pixels to concurrently read out the respective output voltages on at least one readout channel coupled to the respective common readout circuits.   
     
     
         19 . The image sensor controller according to  claim 18 , further comprising means for controlling the common readout circuit to output the stored output voltage of each of the plurality of photodiodes to the at least one readout channel. 
     
     
         20 . The image sensor controller according to  claim 19 , further comprising means for sequentially activating each transfer gate of a plurality of transfer gates in the at least two rows of pixels to sequentially output respective output voltage of each of the plurality of photodiodes in the respective pixel row. 
     
     
         21 . The image sensor controller according to  claim 20 , further comprising transfer gate controlling means for concurrently activating each corresponding transfer gate of the plurality of transfer gates in the at least two rows of pixels, such that the output voltages from the respective photodiodes is concurrently read out on the at least one readout channel as the image sensor controller sequentially activates the respective transfer gates in the at least two rows of pixels. 
     
     
         22 . The image sensor controller of  claim 20 , further comprising connection means for coupling respective transfer gates of the at least two rows of pixels is at an edge of an image area including the at least two rows of pixels. 
     
     
         23 . The image sensor controller of  claim 18 , further comprising a first operational mode controller means for controlling the image sensor in a first operational mode to concurrently sample output values of respective plurality of photodiodes in at least one row of the at least two rows of pixels. 
     
     
         24 . The image sensor controller according to  claim 23 , wherein the first operational mode is a high definition (HD) mode and a second operational mode is an ultra-high definition (UHD) mode. 
     
     
         25 . The image sensor controller according to  claim 24 , further comprising an image generating means for generating image data based on at least one of the individually sampled photodiodes during the UHD mode and the collectively sampled photodiodes during the HD mode. 
     
     
         26 . The image sensor controller according to  claim 22 , further comprising a second operation mode controlling means for controlling the image sensor to sequentially transfer charge between at least two photodiodes of the plurality of photodiodes of the at least one row of the at least two rows of pixels and the respective common readout circuit 
     
     
         27 . The image sensor controller according to  claim 26 , wherein the second operation mode controlling means controls the image sensor to sample photodiode outputs according to a rolling shutter exposure sequence during the UHD mode. 
     
     
         28 . A n  image sensor controller for performing digital sampling of pixel values of an image sensor, the image sensor controller comprising:
 means for reading out a first pixel value from a first pixel on a first pixel row by applying a first signal to the first pixel, the first pixel including a first plurality of photodiodes, and the first pixel value from the first pixel being read out from a first one of the photodiodes of the first plurality of photodiodes; and   means for reading out a first pixel value from a second pixel on a second pixel row by concurrently applying the first signal to the second pixel that includes a second plurality of photodiodes, with the first pixel value from the second pixel being read out from a first one of the photodiodes of the second plurality of photodiodes, and the first and second pixel rows having a linear configuration and a symmetrical layout that is identical to each other.   
     
     
         29 . The image sensor controller of  claim 28 , wherein the first pixel row is adjacent to the second pixel row, and the first pixel is adjacent to the second pixel. 
     
     
         30 . The image sensor controller of  claim 29 , wherein the first one of the photodiodes of the first plurality of photodiodes and the first one of the photodiodes of the second plurality of photodiodes are on different columns. 
     
     
         31 . The image sensor controller of  claim 29 , wherein the first pixel value from the first pixel is read out during a first clock cycle, wherein the first pixel value from the second pixel is read out during a second clock cycle, and the first clock cycle and the second clock cycles are consecutive clock cycles. 
     
     
         32 . The image sensor controller of  claim 28 , further comprising:
 means for reading out a second pixel value from the first pixel by applying a second signal to the first pixel, the second pixel value from the first pixel being read out from a second one of the photodiodes of the first plurality of photodiodes; and   means for reading out a second pixel value from the second pixel by concurrently applying the second signal to the second pixel, the second pixel value from the second pixel being read out from a second one of the photodiodes of the second plurality of photodiodes.   
     
     
         33 . The image sensor controller of  claim 32 , wherein the second one of the photodiodes of the first plurality of photodiodes and the second one of the photodiodes of the second plurality of photodiodes are on different columns. 
     
     
         34 . The image sensor controller of  claim 32 , wherein the second pixel value from the first pixel is read out during a first clock cycle, and wherein the second pixel value from the second pixel is read out during a second clock cycle, and the first clock cycle and the second clock cycles being consecutive clock cycles. 
     
     
         35 . The image sensor controller according to  claim 28 , further comprising means for sequentially activating each transfer gate of a plurality of transfer gates in the first and second pixel rows to sequentially output respective pixel values of each of the plurality of photodiodes in the respective pixel row. 
     
     
         36 . The image sensor controller according to  claim 35 , further comprising means for concurrently activating each corresponding transfer gate of the plurality of transfer gates in the first and second pixel rows, such that the pixel values from the respective photodiodes is concurrently read out on at least one readout channel as the image sensor controller sequentially activates the respective transfer gates in the first and second pixel rows. 
     
     
         37 . The image sensor controller of  claim 36 , further comprising connection means for coupling respective transfer gates of the first and second pixel rows at an edge of an image area including the first and second pixel rows.