Address space management with respect to a coherent accelerator processor interface architecture

Abstract

Disclosed aspects relate to address space management with respect to a Coherent Accelerator Processor Interface (CAPI) architecture. A shared CAPI component may be established to access a plurality of address spaces of a plurality of assets. The plurality of assets may include both a first asset which corresponds to a first address space of the plurality of address spaces and a second asset which corresponds to a second address space of the plurality of address spaces. A request may be detected to process a set of data and route a set of processed data from the first asset to the second asset. The set of data may be processed to form the set of processed data. The set of processed data may be routed from the first address space to the second address space to fulfill the request.

What is claimed is: 
     
         1 . A method for processing data in an accelerator pipeline, the accelerator pipeline including a plurality of accelerator nodes, each accelerator node being a field-programmable gate array (FPGA) programmed with a separate Coherence Accelerator Processor Interface (CAPI) architecture, each CAPI architecture comprising a plurality of address spaces shared among the corresponding FPGA and a plurality of corresponding threads to create a shared CAPI context, the method comprising:
 storing, by a first thread of a first plurality of threads and within a first shared CAPI context, data to be processed in a first address space of a first plurality of address spaces shared among a first FPGA of a first accelerator node of the accelerator pipeline and the first plurality of threads such that the data is directly accessible by the first plurality of threads and the first FPGA;   obtaining, by the first FPGA, the data from the first address space;   processing, by the first FPGA, the data;   storing, by the first FPGA, the processed data in a second address space of the first plurality of address spaces such that the processed data is directly accessible by the first plurality of threads and the first FPGA; and   transferring the processed data from the first accelerator node to a second accelerator node of the accelerator pipeline whereby the transferred data becomes directly accessible, within a second shared CAPI context, to a second FPGA of the second accelerator node and a second plurality of threads sharing a second plurality of address spaces among each other and the second FPGA.