Programmable sequence controller for successive approximation register analog to digital converter

Abstract

The disclosure includes an analog to digital converter (ADC) comprising a successive approximation register (SAR) unit including a capacitive network to take a sample of an analog signal and a comparator to approximate a digital value based on the analog signal sample via successive comparison. The disclosure also includes a programmable sequencer. The sequencer includes a control memory containing control signal states indicating control signals to operate the SAR unit. The sequencer also includes a program memory including sequence instructions defining a duty cycle for the SAR unit by referencing the control signal states in the control memory. The sequencer also includes a processing circuit to apply control signals according to the control signal states in an order defined by the sequence instructions to manage a sequence of operations at the SAR unit according to the duty cycle to control the ADC.

We claim: 
     
         1 . An analog to digital converter comprising:
 an input for receiving an analog signal;   a capacitive network configured to store a sample of the analog signal;   a successive approximation register;   a comparator structured to compare the sample of the analog signal stored in the capacitive network to a value stored in the successive approximation register; and   a programmable sequencer including at least one memory, the programmable sequencer configured to generate control signals that control operation of the successive approximation register.   
     
     
         2 . The analog to digital converter of  claim 1  further comprising:
 an output coupled to the successive approximation register and structured to deliver a digital representation of the analog signal from the analog to digital converter. 
 
     
     
         3 . The analog to digital converter of  claim 1  in which the programmable sequencer comprises a program memory and a control memory. 
     
     
         4 . The analog to digital converter of  claim 3  in which the program memory of the programmable sequencer is configured to store at least two sequence instructions. 
     
     
         5 . The analog to digital converter of  claim 4  in which the programmable sequencer is structured to use the at least two stored sequence instructions to obtain control signal states from the control memory. 
     
     
         6 . The analog to digital converter of  claim 5  in which the programmable sequencer is structured to generate the control signals from a sequence of the stored control states. 
     
     
         7 . The analog to digital converter of  claim 1  in which one of the control signals is structured to cause the analog to digital converter to align the sample of the analog signal to a clock edge. 
     
     
         8 . The analog to digital converter of  claim 1  in which one of the control signals is structured to cause the analog to digital converter to initialize bits in the successive approximation register. 
     
     
         9 . The analog to digital converter of  claim 1  in which one of the control signals is structured to cause the analog to digital converter to power down a portion of the analog to digital converter. 
     
     
         10 . The analog to digital converter of  claim 1  in which one of the control signals is structured to cause the analog to digital converter to power down the successive approximation register. 
     
     
         11 . An audio channel processor in an audio processing microchip, the audio channel processor comprising:
 an input for accepting an analog waveform;   a preamplifier for modifying an amplitude of the analog waveform;   a capacitive network configured to store a sample of the modified analog signal;   a successive approximation register;   a comparator structured to compare the sample of the analog signal stored in the capacitive network to a value stored in the successive approximation register; and   a programmable sequencer including at least one memory, the programmable sequencer configured to generate control signals that control operation of the successive approximation register.   
     
     
         12 . The audio channel processor of  claim 11  in which the programmable sequencer further comprises a program memory configured to store at least two sequence instructions. 
     
     
         13 . The audio channel processor of  claim 12  in which the programmable sequencer is structured to use the at least two stored sequence instructions to obtain control signal states from the control memory. 
     
     
         14 . The audio channel processor of  claim 13  in which the programmable sequencer is structured to generate the control signals from a sequence of the stored control states. 
     
     
         15 . The audio channel processor of  claim 14  in which one of the control signals is structured to cause the analog to digital converter to power down a portion of the analog to digital converter. 
     
     
         16 . The audio channel processor of  claim 14  in which one of the control signals is structured to cause the analog to digital converter to power down the successive approximation register. 
     
     
         17 . A method for generating a digital representation of an analog signal, comprising:
 accepting an analog signal at an input;   storing the analog signal in a capacitive network; and   controlling a function of a successive approximation register by a programmable sequencer to compare the stored analog signal to contents of the successive approximation register and output a result of the comparison.   
     
     
         18 . The method according to  claim 17  in which controlling a function of a successive approximation register comprises initializing individual bits within the successive approximation register to a known value. 
     
     
         19 . The method according to  claim 17  in which controlling a function of a successive approximation register comprises powering down the successive approximation register. 
     
     
         20 . The method according to  claim 17  further comprising powering down a most-significant-bit comparator that is coupled to the capacitive network and the successive approximation register.