Laterally diffused mosfet on fully depleted soi

Abstract

A semiconductor device includes a substrate and a first semiconductor layer disposed on the substrate. The semiconductor device also includes a buried oxide layer disposed on the first semiconductor layer. A second semiconductor layer that comprises a first gate region, a drain region, and a source region is disposed on the buried oxide layer. The first gate region is positioned between the source and drain regions. A first shallow trench isolation is disposed between the drain region and the first semiconductor layer. The first shallow trench isolation is extended from the second semiconductor layer to the first semiconductor layer. The semiconductor device further includes a second gate region.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   a first semiconductor layer disposed on the substrate;   a buried oxide layer disposed on the first semiconductor layer;   a second semiconductor layer disposed on the buried oxide layer, wherein the second semiconductor layer comprises a first gate region, a drain region, and a source region, and wherein the first gate region is positioned between the source and the drain regions;   a first shallow trench isolation disposed between the drain region at a first end of the second semiconductor layer and the first semiconductor layer, wherein the first shallow trench isolation is extended from the second semiconductor layer to the first semiconductor layer; and   a second gate region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the second gate region is disposed on the first semiconductor layer away from the second semiconductor layer and between the first shallow trench isolation and a second shallow trench isolation. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the drain region comprises a lightly doped segment and a highly doped segment of a same dopant type, wherein the highly doped segment comprises a larger dopant concentration compared to the lightly doped segment. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the lightly doped segment of the drain region is formed between the first gate region and the highly doped segment of the drain region. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the second semiconductor layer has a first side in contact with the buried oxide layer, and wherein a gate node, a source node, and a drain node are respectively coupled to the first gate region, the source region, and the drain region on a second side of the second semiconductor layer opposite to the first side of the second semiconductor layer. 
     
     
         6 . The semiconductor device of  claim 1 , further comprising:
 a third shallow trench isolation extending from the second semiconductor layer to the first semiconductor layer and disposed between the source region at a second end of the second semiconductor layer and the first semiconductor layer.   
     
     
         7 . The semiconductor device of  claim 6 , wherein the first shallow trench isolation is configured to isolate the drain region from the first semiconductor layer, and wherein a second shallow trench isolation is extended from the second gate region to the first semiconductor layer, and the third shallow trench isolation is configured to isolate the source region from the first semiconductor layer. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the first semiconductor layer is a doped well in the substrate. 
     
     
         9 . The semiconductor device of  claim 1 , further comprising applying a gate voltage to the second gate region to increase a magnitude of a drain to source current in an on-state. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the source region, the drain region, the second gate region, and the first semiconductor layer are n-type doped, and wherein first gate region in not doped. 
     
     
         11 . The semiconductor device of  claim 1 , wherein the source region, the drain region, the second gate region, and the first semiconductor layer are p-type doped, and wherein first gate region in not doped. 
     
     
         12 . The semiconductor device of  claim 1 , wherein a gate node is coupled to the first gate region and the second gate region and is configured to apply a gate voltage to the first gate region and the second gate region. 
     
     
         13 . An apparatus comprising:
 a first semiconductor layer disposed on a first substrate;   a buried oxide layer disposed on the first semiconductor layer;   a second semiconductor layer disposed on the buried oxide layer;   a first gate region, a drain region, and a source region disposed in the second semiconductor layer, wherein the first gate region is positioned between the source and the drain regions;   a first shallow trench isolation disposed between the drain region at a first end of the second semiconductor layer and the first semiconductor layer; and   a second gate region formed on an etched region on the first semiconductor layer.   
     
     
         14 . The apparatus of  claim 13 , further comprising a gate node configured to apply a gate voltage to the first gate region and the second gate region, and wherein an etched section of the buried oxide layer is next to the first shallow trench isolation and farther from the drain region. 
     
     
         15 . The apparatus of  claim 13 , wherein the first shallow trench isolation is extended from the second semiconductor layer to the first semiconductor layer, and wherein the drain region is isolated from the first semiconductor layer by the first shallow trench isolation. 
     
     
         16 . The apparatus of  claim 13 , wherein the drain region comprises a lightly doped segment and a highly doped segment of a same dopant type, wherein the highly doped segment comprises a larger dopant concentration compared to the lightly doped segment, and wherein the lightly doped segment of the drain region is arranged between the first gate region and the highly doped segment of the drain region. 
     
     
         17 . The apparatus of  claim 13 , further comprising a third shallow trench isolation disposed between the source region at a second end of the second semiconductor layer and the first semiconductor layer, wherein the third shallow trench isolation is extended from the second semiconductor layer to the first semiconductor layer, the source region is isolated from the first semiconductor layer by the third shallow trench isolation, and a second shallow trench isolation is extended from the second gate region to the first semiconductor layer. 
     
     
         18 . The apparatus of  claim 17 , wherein the second gate region is disposed between the first shallow trench isolation and the second shallow trench isolation. 
     
     
         19 . A laterally diffused n-type MOSFET device, the device comprising:
 a first gate region configured to be biased by using a positive gate voltage above a predetermined threshold voltage;   a second gate region disposed on an etched region of a first semiconductor layer between a first shallow trench isolation and a second shallow trench isolation and configured to be biased using the positive gate voltage;   a source region; and   a drain region,   wherein:   the first gate region is configured to operate based on an inversion layer generated by using the positive gate voltage to the first gate region; and   the second gate region is configured to operate based on a back bias generated by using the positive gate voltage to the second gate region.   
     
     
         20 . The device of  claim 19 , wherein the first shallow trench isolation is between the drain region at a first end of a second semiconductor layer and the first semiconductor layer disposed beneath the second semiconductor layer, and wherein the inversion layer and the back bias enable flow of a current from the drain region to the source region.