Semiconductor device, method of fabricating the same, and apparatus used in fabrication thereof

Abstract

A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a substrate;   upper impurity regions in upper portions of the substrate;   metal electrodes electrically connected to the upper impurity regions;   metal silicide layers between the metal electrodes and the upper impurity regions; and   a lower impurity region in a lower portion of the substrate,   wherein   the substrate is a P-type substrate;   the upper impurity regions include NMOS impurity regions of an NMOS transistor; and   the NMOS impurity regions include a P-type heavily doped region in the substrate and an N-type halo region under the P-type heavily doped region.   
     
     
         3 . The semiconductor device of  claim 2 , wherein
 the substrate includes an N-type well,   the upper impurity regions include P-type heavily doped source and drain regions of a PMOS transistor and N-type heavily doped source and drain regions of the NMOS transistor,   the PMOS transistor includes an N-type heavily doped body contact region in the N-type well, and   the lower impurity region is a P-type heavily doped lower impurity region.   
     
     
         4 . The semiconductor device of  claim 2 , wherein
 the semiconductor device is a logic device,
 the upper impurity regions include source/drain regions and body contact regions, and 
 the metal silicide layers correspond to interfacial layers between the source/drain regions and the metal layers as well as between the body contact regions and the metal layers. 
   
     
     
         5 . An apparatus comprising:
 a supporter configured to support a wafer;   a temperature/voltage controller configured to control a temperature and a voltage applied to the wafer;   a heat source over the supporter, the heat source configured to emit heat toward the supporter and be controlled by the temperature/voltage controller;   a power source configured to apply a voltage to the wafer and be controlled by the temperature/voltage controller;   an upper lead probe connected to the power source and configured to contact a top surface of the wafer; and   a lower lead probe connected to a ground terminal of the power source and configured to contact a bottom surface of the wafer.   
     
     
         6 . The apparatus of  claim 5 , wherein
 the wafer includes a lower electrode on a top surface thereof and an upper electrode connected to a bottom surface thereof, and   the upper lead probe contacts the lower electrode, and
 the lower lead probe contacts the upper electrode. 
   
     
     
         7 . The apparatus of  claim 5 , wherein the temperature/voltage controller is configured to apply programmed heat and voltage to the wafer through the heat source and the power source in a concurrent time domain. 
     
     
         8 . The apparatus of  claim 5 , further comprising:
 a temperature sensor under the wafer, wherein   the temperature/voltage controller is configured to control an operation of the heat source based on temperature information that is outputted from the temperature sensor.   
     
     
         9 . The apparatus of  claim 5 , wherein
 the apparatus is configured to concentrate impurity ions in the wafer at an interface between an active layer and a metal suicide layer in the wafer, based on emitting heat from the heat source and applying the voltage generated from the power source to the wafer.   
     
     
         10 . A semiconductor device comprising:
 a substrate;   upper impurity regions in upper portions of the substrate;   metal electrodes electrically connected to the upper impurity regions;   metal silicide layers between the metal electrodes and the upper impurity regions; and   a lower impurity region in a lower portion of the substrate,   wherein   impurity ions are concentrated at an interface between the upper impurity regions and the metal silicide layer.   
     
     
         11 . The semiconductor device of  claim 4 , wherein
 the impurity regions comprise silicon (Si), and   the metal silicide layer comprises nickel silicide (NiSix).   
     
     
         12 . The apparatus of  claim 5 , wherein
 the wafer comprises a plurality of semiconductor devices, and   each of the semiconductor devices is fabricated to comprise a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate.   
     
     
         13 . The semiconductor device of  claim 10 , wherein
 the substrate is a P-type substrate;   the upper impurity regions include NMOS impurity regions of an NMOS transistor; and   the NMOS impurity regions include a P-type heavily doped region in the substrate and an N-type halo region under the P-type heavily doped region.   
     
     
         14 . The semiconductor device of  claim 10 , wherein
 the substrate is a P-type substrate,
 the substrate includes an N-type well, 
   the upper impurity regions include P-type heavily doped source and drain regions of a PMOS transistor and N-type heavily doped source and drain regions of an NMOS transistor, the PMOS transistor includes an N-type heavily doped body contact region in the N-type well,
 the NMOS transistor includes a P-type heavily doped body contact region in the substrate and an N-type halo region under the P-type heavily doped region in the substrate, and
 the lower impurity region is a P-type heavily doped lower impurity region. 
 
   
     
     
         15 . The semiconductor device of  claim 10 , wherein
 the semiconductor device is a logic device,
 the upper impurity regions include source/drain regions and body contact regions, and 
 the metal silicide layers correspond to interfacial layers between the source/drain regions and the metal layers as well as between the body contact regions and the metal layers.