Method of parameter creation

Abstract

According to one embodiment, a method, computer system, and computer program product for creating a plurality of process parameters in a circuit design is provided. The present embodiment of the invention may include receiving one parasitic extraction per layer of a circuit is used to obtain a resistance base factor and a capacitance base factor. The embodiment may further include performing Monte Carlo simulations to determine distributions of capacitance and resistance for each metal layer of the circuit, and creating scalars that scale each of the resistance base factor and the capacitance base factor to a minimum and maximum process limit. Additionally, the embodiment may include defining at least one delay corner using the created scalars, and receiving the results of one or more timing analyses performed using the resistance base factor and the capacitance base factor, and the defined delay corner to determine a delay variability per layer.

What is claimed is: 
     
         1 . A processor-implemented method for creating a plurality of process parameters in a circuit design that improves the speed and efficiency of the circuit design process, the method comprising:
 providing, to a parasitic extractor, one or more inputs comprising factors relating to the metal variation of one or more layers of a circuit, wherein the one or more factors are selected from a group consisting of a nominal wire thickness, a wire width, a via height above, and a via height below;   receiving one or more parasitic extractions from the parasitic extractor which model all of one or more resistive values and one or more capacitive values for each of one or more segments of each of the one or more layers;   performing a plurality of up-front Monte Carlo simulations on the one or more parasitic extractions;   constructing one or more histograms of the one or more capacitance values and the one or more resistance values of each of the one or more layers from the plurality of Monte Carlo simulations by plotting one or more variations within three standard deviations of one or more nominal points to form one or more distribution limits;   creating, based on the one or more histograms, a plurality of scalars representing one or more per-layer resistance distribution limits and one or more capacitance distribution limits that scale each of a resistance base factor and a capacitance base factor to a minimum process limit and a maximum process limit;   defining at least two delay corners using the created plurality of scalars, where at least one delay corner models timing at a minimum capacitance and a minimum resistance, and at least one delay corner models timing at a maximum capacitance and a minimum resistance;   transmitting, to a timing engine, the created plurality of scalars and the at least two delay corners;   receiving, from the timing engine, a plurality of results of one or more timing analyses performed using the plurality of scalars and the defined at least two delay corners to determine a delay variability per layer;   creating, from the determined delay variability per layer, a vector comprising the accumulation of one or more sensitivities of each of the one or more layers, wherein the created vector contains an overall accumulated delay and a plurality of delay change information; and   fabricating one or more circuits conforming to the one or more process parameters, where the process parameters are based on the created vector.