Semiconductor device
Abstract
A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A display device comprising:
a pixel portion; a first sequential circuit; a second sequential circuit; and a bus line configured to supply an output signal of the first sequential circuit to the pixel portion, wherein the first sequential circuit comprises a first output terminal electrically connected to the second sequential circuit, a second output terminal electrically connected to the bus line, a first transistor and a second transistor, wherein one of a source and a drain of the first transistor is electrically connected to the bus line, and the other of the source and the drain of the first transistor is configured to be supplied with a first clock signal, wherein one of a source and a drain of the second transistor is electrically connected to the first output terminal, and the other of the source and the drain of the second transistor is configured to be supplied with a second clock signal, wherein the first transistor and the second transistor are n-channel transistors, and wherein the low-level potential of the first clock signal is higher than the low-level potential of the second clock signal.
2 . The display device according to claim 1 wherein the display device is a liquid crystal device.
3 . The display device according to claim 1 wherein the display device is a light emitting device.
4 . The display device according to claim 1 wherein the first transistor is normally on.
5 . A display device comprising:
a pixel portion; a first sequential circuit; a second sequential circuit; and a bus line configured to supply an output signal of the first sequential circuit to the pixel portion, wherein the first sequential circuit comprises a first output terminal electrically connected to the second sequential circuit, a second output terminal electrically connected to the bus line, a first transistor and a second transistor, wherein one of a source and a drain of the first transistor is electrically connected to the bus line, and the other of the source and the drain of the first transistor is configured to be supplied with a first clock signal, wherein one of a source and a drain of the second transistor is electrically connected to the first output terminal, and the other of the source and the drain of the second transistor is configured to be supplied with a second clock signal, wherein the first transistor and the second transistor are n-channel transistors, wherein the low-level potential of the first clock signal is higher than the low-level potential of the second clock signal, wherein a channel region of the first transistor and the second transistor comprises an oxide semiconductor, and wherein the oxide semiconductor comprises a crystal with a size greater than or equal to 1 nm and less than 10 nm.
6 . The display device according to claim 5 wherein the display device is a liquid crystal device.
7 . The display device according to claim 5 wherein the display device is a light emitting device.
8 . The display device according to claim 5 wherein the first transistor is normally on.
9 . The display device according to claim 5 wherein the oxide semiconductor comprises In, Ga, and Zn.Join the waitlist — get patent alerts
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