Fin-fet devices

Abstract

Fin-FET device is provided including a substrate, fin structures protruding from the substrate, and an isolation structure covering a portion of sidewall surfaces of the fin structures with a top surface lower than the fin structures. Gate structures are formed on the isolation layer across the fin structures. Doped source/drain regions are formed in the fin structures on opposite sides of each gate structure. A metal contact layer is formed on entire surfaces of the doped source/drain regions and converted from a metal layer through a reaction annealing process. A dielectric layer is formed on the metal contact layer and the gate structures. A top surface of the dielectric layer is higher than the top surfaces of the gate structures. Conductive plugs are formed through the dielectric layer and in contact with a portion of the metal contact layer.

What is claimed is: 
     
         1 . A Fin-FET device, composing:
 a substrate;   a plurality of fin structures protruding from the substrate;   an isolation structure covering a portion of sidewall surfaces of the fin structures with a top surface of the isolation structure lower than top surfaces of the fin structures;   a plurality of gate structures formed on the isolation layer across the fin structures, wherein the gate structures cover a portion of the sidewall and the top surfaces of the fin structures;   a plurality of doped source/drain regions formed in the fin structures on opposite sides of each gate structure;   a metal contact layer formed on entire surfaces of the doped source/drain regions and converted from a metal layer through a reaction annealing process;   a dielectric layer formed on the metal contact layer and the gate structures, wherein a top surface of the dielectric layer is higher than the top surfaces of the gate structures; and   a plurality of conductive plugs formed through the dielectric layer and in contact with a portion of the metal contact layer.   
     
     
         2 . The Fin-FET device according to  claim 1 , wherein.
 the reaction annealing process performed to convert the metal layer into the metal contact layer is a laser annealing process; and   an anneal temperature used in the laser annealing process is in a range of approximately 800° C. to 880° C.   
     
     
         3 . The Fin-FET device according to  claim 1 , wherein:
 the metal layer is made of one or more of Ni, W, Ti, Ta, Pt, and Co.   
     
     
         4 . The Fin-FET device according to  claim 1 , wherein:
 the metal layer covers entire surfaces of the doped source/drain regions.   
     
     
         5 . The Fin-FET device according to  claim 1 , wherein:
 the gate structures are metal gate structures.   
     
     
         6 . The Fin-FET device according to  claim 1 , further including:
 a cap layer formed on the gate structures, wherein:   a thickness of the cap layer is in a range of approximately 5 Å to 35 Å; and   the cap layer is made of one of SiN x  and BN.   
     
     
         7 . The Fin-FET device according to  claim 1 , wherein:
 a plurality of sidewall spacers covering sidewall surfaces of the gate structures are formed; and   the metal layer is also formed on the sidewall spacers.   
     
     
         8 . The Fin-FET device according to  claim 7 , wherein:
 the doped source/drain regions include a stress layer formed in the fin structures next to each sidewall spacer.   
     
     
         9 . The Fin-FET device according to  claim 1 , wherein:
 the Fin-FET device includes a plurality of N-type metal-oxide-semiconductor (NMOS) transistors, P-type metal-oxide-semiconductor (PMOS) transistors, and complementary metal-oxide-semiconductor (CMOS) transistors.   
     
     
         10 . The Fin-FET device according to  claim 1 , wherein:
 the dielectric layer includes a first dielectric layer and a second dielectric layer formed on the second dielectric layer; and   a density of the first dielectric layer is larger than a density of the second dielectric layer.   
     
     
         11 . The Fin-FET device according to  claim 1 , wherein:
 the metal layer is formed directly on top surfaces of the doped source/drain regions.   
     
     
         12 . The Fin-FET device according to  claim 1 , wherein:
 the metal contact layer is formed on at least a portion of side surfaces of the doped source/drain regions.   
     
     
         13 . The Fin-FET device according to  claim 1 , wherein:
 a thickness of the metal layer is in a range of approximately 50 Å to 200 Å.