Write suppression in non-volatile memory

Abstract

Techniques are disclosed for write suppression to improve endurance rating of non-volatile memories, such as QLC-NAND SSDs or other relatively slow, low endurance non-volatile memories. In an embodiment, an SSD is configured with a fast frontend non-volatile memory, a relatively slow lower endurance backend non-volatile memory, and a frontend manager that selectively transfers data from the fast memory to the slow memory based on transfer criteria. In operation, write data from the host is initially written to the fast memory by the frontend manager. The data is moved from the fast memory to the slow memory in bands. For each data band stored in the fast memory, the frontend manager tracks invalid data counts and data age. Only bands that still remain valid are transferred to the slow memory. After a given band has been fully transferred, it is erased and re-usable for other incoming writes by the frontend manager.

1 - 25 . (canceled) 
     
     
         26 . A method for suppressing writes to a quad level cell (QLC) non-volatile memory, the method comprising:
 receiving, from a host, data to be written to the QLC non-volatile memory;   writing the data to a fast non-volatile memory for storing one or more bands of data;   evaluating the one or more bands of data of the fast non-volatile memory to identify a target band for eviction from the fast non-volatile memory to the QLC non-volatile memory; and   selectively moving data of the target band from the fast non-volatile memory to the QLC non-volatile memory, wherein only valid data of the target band is moved from the fast non-volatile memory to the QLC non-volatile memory.   
     
     
         27 . The method of  claim 26 , wherein evaluating a given band of the fast non-volatile memory includes: evaluating age of data included in the given band; and determining the number of invalid data blocks within the given band. 
     
     
         28 . The method of  claim 26 , wherein only after a given band has been fully moved to the QLC non-volatile memory, the given band is erased and made available for storing other incoming data. 
     
     
         29 . The method of  claim 26 , further comprising: retaining, in the fast non-volatile memory, one or more logical blocks of data of a given band, so as to eliminate need to store those one or more logical blocks of data in the QLC non-volatile memory, thereby exposing part of the fast non-volatile memory to the host. 
     
     
         30 . The method of  claim 29 , wherein exposing part of the fast non-volatile memory to the host effectively provides a concatenation of the fast non-volatile memory and the QLC non-volatile memory. 
     
     
         31 . The method of  claim 30 , wherein the QLC non-volatile memory is 8 Gigabytes (GB) or greater. 
     
     
         32 . The method of  claim 26 , wherein a given band of data comprises one or more logical blocks of data. 
     
     
         33 . The method of  claim 32 , wherein a logical block of data is smaller than a band of data, such that a given band of data comprises multiple logical blocks of data. 
     
     
         34 . A computer program product including one or more non-transitory machine-readable mediums encoded with instructions that when executed by one or more processors cause a process to be carried out for suppressing writes to a quad level cell (QLC) non-volatile memory, the process comprising:
 receiving, from a host, data to be written to the QLC non-volatile memory;   writing the data to a fast non-volatile memory for storing one or more bands of data;   evaluating the one or more bands of data of the fast non-volatile memory to identify a target band for eviction from the fast non-volatile memory to the QLC non-volatile memory; and   selectively moving data of the target band from the fast non-volatile memory to the QLC non-volatile memory, wherein only valid data of the target band is moved from the fast non-volatile memory to the QLC non-volatile memory.   
     
     
         35 . The computer program product of  claim 34 , wherein evaluating a given band of the fast non-volatile memory includes: evaluating age of data included in the given band; and determining the number of invalid data blocks within the given band. 
     
     
         36 . The computer program product of  claim 34 , wherein only after a given band has been fully moved to the QLC non-volatile memory, the given band is erased and made available for storing other incoming data. 
     
     
         37 . The computer program product of  claim 34 , the process further comprising: retaining, in the fast non-volatile memory, one or more logical blocks of data of a given band, so as to eliminate need to store those one or more logical blocks of data in the QLC non-volatile memory, thereby exposing part of the fast non-volatile memory to the host. 
     
     
         38 . The computer program product of  claim 37 , wherein exposing part of the fast non-volatile memory to the host effectively provides a concatenation of the fast non-volatile memory and the QLC non-volatile memory. 
     
     
         39 . The computer program product of  claim 38 , wherein the QLC non-volatile memory is 8 Gigabytes (GB) or greater. 
     
     
         40 . The computer program product of  claim 34 , wherein a given band of data comprises one or more logical blocks of data. 
     
     
         41 . The computer program product of  claim 40 , wherein a logical block of data is smaller than a band of data, such that a given band of data comprises multiple logical blocks of data. 
     
     
         42 . A system for suppressing writes to a quad level cell (QLC) non-volatile memory, the system comprising:
 one or more memory structures encoded with instructions that when executed by one or more processors cause a process to be carried out for suppressing writes to a quad level cell (QLC) non-volatile memory; and   one or more processors for executing the instructions to receive, from a host, data to be written to the QLC non-volatile memory;
 write the data to a fast non-volatile memory for storing one or more bands of data; 
 evaluate the one or more bands of data of the fast non-volatile memory to identify a target band for eviction from the fast non-volatile memory to the QLC non-volatile memory, said evaluation including evaluating age of data included in the given band, and determining the number of invalid data blocks within the given band; 
 selectively mov data of the target band from the fast non-volatile memory to the QLC non-volatile memory, wherein only valid data of the target band is moved from the fast non-volatile memory to the QLC non-volatile memory; and 
 retain, in the fast non-volatile memory, one or more logical blocks of data of a given band, so as to eliminate need to store those one or more logical blocks of data in the QLC non-volatile memory, thereby exposing part of the fast non-volatile memory to the host. 
   
     
     
         43 . The system of  claim 42 , further comprising the QLC non-volatile memory and the fast non-volatile memory. 
     
     
         44 . The system of  claim 42 , wherein a given band of data comprises one or more logical blocks of data, and a logical block of data is smaller than a band of data, such that a given band of data comprises multiple logical blocks of data, and wherein only after a given band has been fully moved to the QLC non-volatile memory, the given band is erased and made available for storing other incoming data. 
     
     
         45 . A solid state memory device comprising the system of  claim 42 .