Vertical resistor buffered multiplexer buskeeper

Abstract

A buffered multiplexer includes a multiplexer having N multiplexer inputs each input selectively coupleable to a single multiplexer output. A non-inverting buffer has an input coupled to the multiplexer output and an output forming the output node of the buffered multiplexer. At least one vertical resistor is coupled between the input and the output of the non-inverting buffer.

What is claimed is: 
     
         1 . A buffered multiplexer comprising:
 a multiplexer having N multiplexer inputs each input selectively coupleable to a single multiplexer output;   a non-inverting buffer having an input and an output, the input coupled to the multiplexer output; and   at least one vertical resistor coupled between the input and the output of the non-inverting buffer.   
     
     
         2 . The buffered multiplexer of  claim 1  wherein the at least one vertical resistor is formed as an unprogrammed antifuse. 
     
     
         3 . The buffered multiplexer of  claim 1  wherein the at least one vertical resistor is formed as a virgin ReRAM device. 
     
     
         4 . The buffered multiplexer of  claim 1  wherein the at least one vertical resistor is formed as a layer of a high-resistance metal compound. 
     
     
         5 . The buffered multiplexer of  claim 1  wherein the non-inverting buffer includes a first inverter connected in series with a second inverter. 
     
     
         6 . The buffered multiplexer of  claim 1  wherein the at least one vertical resistor comprises a first vertical resistor connected in series with a second vertical resistor coupled between the input and the output of the non-inverting buffer. 
     
     
         7 . The buffered multiplexer of  claim 6  wherein the first and second vertical resistors are formed as an unprogrammed antifuse. 
     
     
         8 . The buffered multiplexer of  claim 6  wherein the first and second vertical resistors are formed as a virgin ReRAM device. 
     
     
         9 . The buffered multiplexer of  claim 6  wherein the first and second vertical resistors are formed as a layer of a high-resistance metal compound. 
     
     
         10 . The buffered multiplexer of  claim 6  wherein the non-inverting buffer includes a first inverter connected in series with a second inverter. 
     
     
         11 . A buffered multiplexer comprising:
 a multiplexer having N multiplexer inputs each input selectively coupleable to a single multiplexer output;   a non-inverting buffer having an input and an output, the input coupled to the multiplexer output;   a first parallel circuit including a first pair of vertical resistors connected in parallel, a first end of the first parallel circuit coupled to the output of the non-inverting buffer;   a second parallel circuit including a second pair of vertical resistors connected in parallel, a first end of the second parallel circuit coupled to the input of the non-inverting buffer;   a second end of the first parallel circuit coupled to the second end of the second parallel circuit.   
     
     
         12 . The buffered multiplexer of  claim 11  wherein the first and second pairs of vertical resistors are formed as an unprogrammed antifuse. 
     
     
         13 . The buffered multiplexer of  claim 11  wherein the first and second pairs of vertical resistors are formed as a virgin ReRAM device. 
     
     
         14 . The buffered multiplexer of  claim 11  wherein the first and second vertical resistors are formed as a layer of a high-resistance metal compound. 
     
     
         15 . The buffered multiplexer of  claim 11  wherein the non-inverting buffer includes a first inverter connected in series with a second inverter. 
     
     
         16 . In a multiplexer having a plurality of data inputs selectively coupleable to a data output, a method for preventing the output of the mutiplexer from assuming an undetermined state when none of the data inputs have been selected, the method comprising:
 connecting a non-inverting buffer between the data output of the multiplexer and an output node of the multiplexer coupling the output of the non-inverting buffer; and   coupling a vertical resistor between the input of the non-inverting buffer and the output of the non-inverting buffer, the vertical resistor having a resistance that is low enough to force the output of the multiplexer at the input of non-inverting buffer to assume the state of the output of the non-inverting buffer portion, the resistance being high enough to prevent a time delay impact on the speed of the multiplexer when the signal passed through from one of its inputs has to force the input of the non-inverting buffer to a desired logic level.   
     
     
         17 . The method of  claim 16 , wherein coupling a vertical resistor between the input of the non-inverting buffer and the output of the non-inverting buffer comprises coupling one of an unprogrammed antifuse, a virgin ReRAM device, and a high-resistance metal compound between the input of the non-inverting buffer and the output of the non-inverting buffer.