US2019228987A1PendingUtilityA1
Manufacturing method of semiconductor device
Est. expiryJun 24, 2035(~8.9 yrs left)· nominal 20-yr term from priority
Inventors:Kei Taniguchi
H10W 90/756H10W 90/736H10W 74/00H10W 72/9445H10W 72/5522H10W 72/5449H10W 72/932H10W 72/884H10W 72/075H10W 72/073H10W 72/59H10W 70/042H10W 74/111H10W 70/457H10W 70/424H10W 70/411H10W 74/127H10W 74/01H01L 2224/06135H01L 23/49582H01L 21/4828H01L 23/49503H01L 23/49548H01L 24/73H01L 24/45H01L 2224/32245H01L 2224/49171H01L 2224/73265H01L 2224/92247H01L 24/92H01L 2224/48091H01L 24/32H01L 23/3107H01L 24/48H01L 21/56H01L 24/06H01L 2224/05554H01L 2224/45144H01L 2924/181H10W 72/90H10W 99/00H10W 72/30H10W 72/851H10W 72/50H10W 72/00
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Claims
Abstract
A semiconductor device includes: a chip mounting portion having a lower surface on which a first ditch is formed; a semiconductor chip mounted on an upper surface of the chip mounting portion; a lead electrically connected to a pad of the semiconductor chip through a conductive member; and a sealing body configured to seal the semiconductor chip, wherein the lower surface of the chip mounting portion is exposed from the sealing body, and wherein a plating film is formed on the lower surface including an inside of the first ditch.
Claims
exact text as granted — not AI-modified1 . A semiconductor device comprising:
a chip mounting portion having a lower surface on which a first ditch is formed; a semiconductor chip mounted on an upper surface of the chip mounting portion; a lead electrically connected to a pad of the semiconductor chip through a conductive member; and a sealing body configured to seal the semiconductor chip, wherein the lower surface of the chip mounting portion is exposed from the sealing body, and wherein a plating film is formed on the lower surface including an inside of the first ditch.
2 . The semiconductor device according to claim 1 ,
wherein resin constituting the sealing body is not formed inside the first ditch.
3 . The semiconductor device according to claim 1 ,
wherein the first ditch is formed along an outer peripheral portion of the chip mounting portion.
4 . The semiconductor device according to claim 1 ,
wherein a depth of the first ditch is ½ or less of a thickness of the chip mounting portion.
5 . The semiconductor device according to claim 1 ,
wherein the first ditch has a V-shaped cross section.
6 . The semiconductor device according to claim 1 ,
wherein a second ditch is further formed on the lower surface of the chip mounting portion so as to be spaced apart from the first ditch.
7 . The semiconductor device according to claim 6 ,
wherein the second ditch is formed on an inner side of the chip mounting portion relative to the first ditch.
8 . The semiconductor device according to claim 6 ,
wherein a depth of the first ditch and a depth of the second ditch are both ½ or less of a thickness of the chip mounting portion.
9 . The semiconductor device according to claim 7 ,
wherein a depth of the first ditch is deeper than a depth of the second ditch.
10 . The semiconductor device according to claim 6 ,
wherein the plating film is formed also on an inner wall of the second ditch.
11 . The semiconductor device according to claim 6 ,
wherein resin constituting the sealing body is not formed inside the second ditch.
12 . The semiconductor device according to claim 1 ,
wherein a step portion spaced apart from the first ditch is formed at an outer end of the lower surface of the chip mounting portion.
13 . The semiconductor device according to claim 12 ,
wherein the first ditch is formed on an inner side of the step portion.
14 . The semiconductor device according to claim 12 ,
wherein a depth of the first ditch is shallower than a difference in level of the step portion.
15 . The semiconductor device according to claim 12 ,
wherein a second ditch is formed on an inner side of the first ditch on the lower surface of the chip mounting portion, and a distance between the step portion and a center position of the first ditch is smaller than a distance between the center position of the first ditch and a center position of the second ditch in a cross-sectional view.
16 . The semiconductor device according to claim 12 ,
wherein resin constituting the sealing body is formed inside the step portion.
17 . The semiconductor device according to claim 1 ,
wherein the chip mounting portion has a first side extending in a first direction, a second side crossing the first side, and a corner portion which is an intersection of the first side and the second side, wherein the first ditch includes a first portion parallel to the first side, a second portion parallel to the second side, and a third portion connecting the first portion and the second portion, and wherein a distance between the third portion of the first ditch and the corner portion is longer than a distance between the first portion of the first ditch and the first side, and is longer than a distance between the second portion of the first ditch and the second side.
18 . The semiconductor device according to claim 17 ,
wherein an angle formed by the third portion and the first portion is an obtuse angle, and wherein an angle formed by the third portion and the second portion is an obtuse angle.Join the waitlist — get patent alerts
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