Analog driver with built-in wave shaping

Abstract

An amplifier includes a dynamic bias circuit and an amplification circuit coupled to the dynamic bias circuit. The dynamic bias circuit includes a plurality of transistors coupled to a plurality of resistors. The dynamic bias circuit is configured to generate a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of an input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal. The amplification circuit is configured to receive the bias current and amplify the input signal based on the bias current to generate an output signal that has a higher slew rate for a falling signal than for a rising signal.

What is claimed is: 
     
         1 . An amplifier, comprising:
 a dynamic bias circuit including a plurality of transistors coupled to a plurality of resistors, the dynamic bias circuit configured to generate a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of an input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal; and   an amplification circuit coupled to the dynamic bias circuit, the amplification circuit configured to receive the bias current and amplify the input signal based on the bias current to generate an output signal that has a higher slew rate for a falling signal than for a rising signal.   
     
     
         2 . The amplifier of  claim 1 , wherein the plurality of transistors includes:
 a first transistor that comprises a first gate, a first source, and a first drain, the first gate connected to a first differential input of the input signal, the first drain connected to ground, and the first source connected to a first resistor;   a second transistor that comprises a second gate, a second source, and a second drain, the second gate coupled to a second differential input of the input signal, the second drain connected to ground, and the second source connected to a second resistor;   a third transistor that comprises a third gate, a third source, and a third drain, the third source connected to the first resistor; and   a fourth transistor that comprises a fourth gate, a fourth source, and a fourth drain, the fourth source connected to the second resistor and the fourth gate connected to the third gate.   
     
     
         3 . The amplifier of  claim 2 , wherein the plurality of transistors further includes:
 a fifth transistor that comprises a fifth gate, a fifth source, and a fifth drain, the fifth gate connected to the first differential input and the fifth drain connected to ground;   a sixth transistor that comprises a sixth gate, a sixth source, and a sixth drain, the sixth gate coupled to the second differential input and the sixth drain connected to ground;   a seventh transistor that comprises a seventh gate, a seventh source, and a seventh drain, the seventh source connected to the fifth source; and   an eighth transistor that comprises an eighth gate, an eighth source, and an eighth drain, the eighth source connected to the sixth source and the eighth gate connected to the seventh gate.   
     
     
         4 . The amplifier of  claim 3 , wherein the first, second, fifth, and sixth transistors are p-channel metal oxide semiconductor (PMOS) transistors and the third, fourth, seventh, and eighth transistors are n-channel metal oxide semiconductor (NMOS) transistors. 
     
     
         5 . The amplifier of  claim 1 , wherein the output signal is in a single edge nibble transmission (SENT) protocol. 
     
     
         6 . The amplifier of  claim 1 , wherein the input signal is an analog signal received from a pressure sensor and the output signal is a digital signal. 
     
     
         7 . A circuit, comprising:
 a plurality of resistors; and   a plurality of transistors coupled to the plurality of resistors, the plurality of transistors configured to generate a bias current with a magnitude that increases in response to a first transistor of the plurality of transistors receiving a falling edge of an input signal and decreases in response to the first transistor receiving a rising edge of the input signal.   
     
     
         8 . The circuit of  claim 7 , wherein:
 the plurality of transistors further includes a second transistor, a third transistor, and a fourth transistor;   the first transistor comprises a first gate, a first source, and a first drain, the first gate connected to a first differential input of the input signal, the first drain connected to ground, and the first source connected to a first resistor of the plurality of resistors;   the second transistor comprises a second gate, a second source, and a second drain, the second gate coupled to a second differential input of the input signal, the second drain connected to ground, and the second source connected to a second resistor of the plurality of resistors;   the third transistor that comprises a third gate, a third source, and a third drain, the third source connected to the first resistor; and   the fourth transistor that comprises a fourth gate, a fourth source, and a fourth drain, the fourth source connected to the second resistor and the fourth gate connected to the third gate.   
     
     
         9 . The circuit of  claim 8 , wherein the plurality of transistors further includes:
 a fifth transistor that comprises a fifth gate, a fifth source, and a fifth drain, the fifth gate connected to the first differential input and the fifth drain connected to ground;   a sixth transistor that comprises a sixth gate, a sixth source, and a sixth drain, the sixth gate coupled to the second differential input and the sixth drain connected to ground;   a seventh transistor that comprises a seventh gate, a seventh source, and a seventh drain, the seventh source connected to the fifth source; and   an eighth transistor that comprises an eighth gate, an eighth source, and an eighth drain, the eighth source connected to the sixth source and the eighth gate connected to the seventh gate.   
     
     
         10 . The circuit of  claim 7 , wherein the input signal is an analog signal received from a pressure sensor. 
     
     
         11 . A method for generating a digital output signal, comprising:
 receiving, by a dynamic bias circuit, an input signal from a sensor;   generating, by the dynamic bias circuit, a bias current with a magnitude that increases in response to the dynamic bias circuit receiving a falling edge of the input signal and decreases in response to the dynamic bias circuit receiving a rising edge of the input signal; and   amplifying, by an amplification circuit, the input signal based on the bias current to generate the digital output signal that has a higher slew rate for a falling signal than for a rising signal.