Three dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns.

1 . A three-dimensional semiconductor memory device, comprising;
 a stacked structure including a plurality of conductive patterns vertically stacked on a substrate;   a selection structure including first, second, and third selection conductive patterns sequentially stacked on the stacked structure;   a channel structure penetrating the selection structure and the stacked structure to connect to the substrate;   a bit line crossing the selection structure; and   a conductive pad disposed on the channel structure to electrically connect the bit line to the channel structure,   wherein the first and second selection conductive patterns are connected in common to a string selection line, and   the third selection conductive pattern is connected to a dummy string selection line.   
     
     
         2 . The device of  claim 1 , wherein the bottom surface of the conductive pad is positioned between top and bottom surfaces of the third selection conductive pattern. 
     
     
         3 . The device of  claim 1 , wherein the bottom surface of the conductive pad is positioned between a bottom surface of third selection conductive pattern and a top surface of the second selection conductive pattern. 
     
     
         4 . The device of  claim 1 , wherein the string selection line is electrically separated from the dummy string selection line. 
     
     
         5 . The device of  claim 1 , wherein the conductive pad includes impurities of a first conductivity type, and
 wherein the channel structure includes a channel impurity region having impurities of a second conductivity type and positioned adjacent to at least one of the plurality of selection conductive patterns.   
     
     
         6 . The device of  claim 5 , wherein the bottom surface of the conductive pad is separated from the channel impurity region. 
     
     
         7 . The device of  claim 5 , wherein, in the channel impurity region, an impurity concentration is maximum at a position between the first and second selection conductive patterns. 
     
     
         8 . The device of  claim 1 , wherein the first, second, and third selection conductive patterns has substantially the same thickness as that of at least one of the plurality of conductive patterns. 
     
     
         9 . The device of  claim 1 , further comprising:
 a vertical insulating layer vertically extending from a region between the channel structure and the stacked structure to a region between the channel structure and the selection structure; and   a horizontal insulating layer provided between the vertical insulating layer and the channel structure and extended to cover top and bottom surfaces of the selection conductive patterns and the conductive patterns.   
     
     
         10 . The device of  claim 9 , wherein the vertical insulating layer vertically extends from a region between the channel structure and the selection structure to cover a sidewall of the conductive pad. 
     
     
         11 . A three-dimensional semiconductor memory device, comprising:
 a first selection structure extending along a first direction and including a plurality of first selection conductive patterns vertically stacked on a substrate;   a second selection structure adjacent to the first selection structure and including a plurality of second selection conductive patterns vertically stacked on the substrate;   first and second channel structures penetrating the first and second selection structures, respectively;   an upper interconnection line crossing the first and second selection structures; and   first and second conductive pads provided on the first and second channel structures, respectively, to electrically connect the upper interconnection line to the first and second channel structures,   wherein bottom surfaces of the first and second conductive pads are positioned below top surfaces of the uppermost first and second selection conductive patterns,   wherein the first conductive pad includes impurities of a first conductivity type, and the first channel structure comprises a channel impurity region having impurities of a second conductivity type and positioned adjacent to the first selection conductive patterns,   wherein the bottom surface of the first conductive pad is separated from the channel impurity region.   
     
     
         12 . The device of  claim 11 , further comprising:
 a first string selection line connected in common to the connecting the plurality of first selection conductive patterns; and   a second string selection line connected in common to the plurality of second selection conductive patterns to each other.   
     
     
         13 . The device of  claim 12 , wherein the first string selection line is electrically separated from the second string selection line. 
     
     
         14 . The device of  claim 11 , further comprising:
 a dummy string line connected to the uppermost first selection conductive pattern of the plurality of first selection conductive patterns and the uppermost second selection conductive pattern of the plurality of second selection conductive patterns;   a first string selection line connected to the remaining selection conductive patterns of the plurality of first selection conductive patterns;   a second string selection line connected to the remaining second selection conductive patterns of the plurality of second selection conductive patterns.   
     
     
         15 . The device of  claim 11 , further comprising a stacked structure between the substrate and the first selection structure, the stacked structure including a plurality of conductive patterns vertically stacked on a substrate,
 wherein the first and second selection conductive patterns has substantially the same thickness as that of at least one of the plurality of conductive patterns.