Three-dimensional stacked vertical transport field effect transistor logic gate with buried power bus

Abstract

Techniques facilitating three-dimensional stacked vertical transport field effect transistor logic gates with buried power bus are provided. A logic device can comprise a plate and a first vertical transport field effect transistor formed over and adjacent the plate. The logic device can also comprise a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor. The plate can be a power layer and can be continuous within regions of the device that utilize a common voltage. The plate can be contacted from a surface of the device at intervals corresponding to the regions of common voltage. The plate can be electrically connected to ground. Alternatively, the plate can be electrically connected to a power supply.

What is claimed is: 
     
         1 . A device, comprising:
 a plate formed on a substrate;   a first vertical transport field effect transistor formed over and adjacent the plate; and   a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor, wherein the plate is a power layer and is continuous within regions of the device that utilize a common voltage.   
     
     
         2 . The device of  claim 1 , wherein the plate comprises an isolation region that separates a first region of the device that utilizes a first voltage from a second region of the device that utilizes a second voltage. 
     
     
         3 . The device of  claim 1 , wherein the plate is contacted from a surface of the device at intervals corresponding to the regions of common voltage. 
     
     
         4 . The device of  claim 3 , wherein the first vertical transport field effect transistor is a p-channel field effect transistor and the second vertical transport field effect transistor is an n-channel field effect transistor, and wherein the plate is electrically connected to a power supply. 
     
     
         5 . The device of  claim 3 , wherein the first vertical transport field effect transistor is an n-channel field effect transistor and the second vertical transport field effect transistor is a p-channel field effect transistor, and wherein the plate is electrically connected to ground. 
     
     
         6 . The device of  claim 1 , further comprising:
 a first bonding film on the first vertical transport field effect transistor; and   a second bonding film coupled to the second vertical transport field effect transistor and affixing the second vertical transport field effect transistor to the first vertical transport field effect transistor.   
     
     
         7 . The device of  claim 6 , further comprising:
 one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.   
     
     
         8 . The device of  claim 1 , wherein the substrate is comprised of indium gallium arsenide or indium phosphide. 
     
     
         9 . A semiconductor chip, comprising:
 a plate formed on a substrate;   a first vertical transport field effect transistor formed on the plate; and   a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor, wherein the plate is a power layer and is continuous within regions of the semiconductor chip that utilize a common voltage.   
     
     
         10 . The semiconductor chip of  claim 9 , wherein the plate is contacted from a surface of the semiconductor chip at intervals corresponding to the regions of common voltage. 
     
     
         11 . The semiconductor chip of  claim 10 , wherein the first vertical transport field effect transistor is a p-channel field effect transistor and the second vertical transport field effect transistor is an n-channel field effect transistor. 
     
     
         12 . The semiconductor chip of  claim 11 , wherein the plate is electrically connected to a power supply voltage, and wherein the substrate is comprised of silicon dioxide. 
     
     
         13 . The semiconductor chip of  claim 10 , wherein the first vertical transport field effect transistor is an n-channel field effect transistor and the second vertical transport field effect transistor is a p-channel field effect transistor. 
     
     
         14 . The semiconductor of  claim 13 , wherein the plate is electrically connected to ground. 
     
     
         15 . The semiconductor chip of  claim 9 , further comprising:
 a first bonding film deposited on the first vertical transport field effect transistor.   
     
     
         16 . The semiconductor chip of  claim 15 , further comprising:
 a second bonding film formed with the second vertical transport field effect transistor, wherein the second bonding film affixes the second vertical transport field effect transistor to the first vertical transport field effect transistor.   
     
     
         17 . A semiconductor chip, comprising:
 a substrate having at least one isolation region;   a plate formed on a portion of the substrate other than the at least one isolation region;   a first vertical transport field effect transistor formed on the plate; and   a second vertical transport field effect transistor stacked on the first vertical transport field effect transistor, wherein the plate is a power layer and is continuous within regions of the semiconductor chip that utilize a common voltage.   
     
     
         18 . The semiconductor chip of  claim 17 , wherein the first vertical transport field effect transistor is a p-channel field effect transistor and the second vertical transport field effect transistor is an n-channel field effect transistor. 
     
     
         19 . The semiconductor chip of  claim 17 , further comprising:
 a first bonding film deposited on the first vertical transport field effect transistor; and   a second bonding film formed with the second vertical transport field effect transistor.   
     
     
         20 . The semiconductor chip of  claim 19 , wherein the second bonding film affixes the second vertical transport field effect transistor to the first vertical transport field effect transistor.