Low-resistivity metallic interconnect structures with self-forming diffusion barrier layers

Abstract

Methods for fabricating low-resistivity metallic interconnect structures with self-forming diffusion barrier layers are provided, as well as semiconductor devices comprising low-resistivity metallic interconnect structures with self-formed diffusion barrier layers. For example, a semiconductor device includes a dielectric layer disposed on a substrate, an opening etched in the dielectric layer, a metallic liner layer covering sidewall and bottom surfaces of the opening in the dielectric layer, copper material filling the opening to form an interconnect structure, and a self-formed diffusion barrier layer formed in the sidewall surfaces of the opening of the dielectric layer. The self-formed diffusion barrier layer includes manganese atoms which are diffused into the sidewall surfaces of the dielectric layer.

We claim: 
     
         1 . A device, comprising:
 a dielectric layer disposed on a substrate;   an opening etched in the dielectric layer;   a metallic liner layer covering sidewall and bottom surfaces of the opening in the dielectric layer;   metallic material filling the opening to form an interconnect structure; and   a self-formed diffusion barrier layer embedded in the sidewall surfaces of the opening of the dielectric layer, wherein the self-formed diffusion barrier layer comprises manganese atoms which are diffused into the sidewall surfaces of the opening of the dielectric layer.   
     
     
         2 . The device of  claim 1 , wherein the self-formed barrier diffusion layer comprises one of silicon manganese, manganese carbonate, and manganese oxide. 
     
     
         3 . The device of  claim 1 , further comprising a diffusion barrier layer disposed on the bottom surface of the opening in the dielectric layer. 
     
     
         4 . The device of  claim 3 , wherein the diffusion barrier layer comprises at least one of tantalum, tantalum nitride, titanium, and titanium nitride. 
     
     
         5 . The device of  claim 1 , wherein the metallic liner layer comprises cobalt, and wherein the metallic material comprises copper. 
     
     
         6 . The device of  claim 1 , wherein the dielectric layer comprises an interlayer dielectric layer of a back-end-of-line structure. 
     
     
         7 . The device of  claim 1 , wherein the opening in the dielectric layer comprises a via opening which defines a via interconnect. 
     
     
         8 . The device of  claim 1 , wherein the opening in the dielectric layer comprises a trench opening which defines a wire interconnect. 
     
     
         9 . The device of  claim 1 , wherein the opening in the dielectric layer comprises a dual damascene opening which comprises a via opening and a trench opening disposed above the via opening. 
     
     
         10 . A device, comprising:
 a dielectric layer disposed on a substrate;   an opening etched in the dielectric layer;   a metallic liner layer covering sidewall and bottom surfaces of the opening in the dielectric layer;   a metallic seed layer disposed on the metallic liner layer, wherein the metallic seed layer comprises manganese;   metallic material filling the opening to form an interconnect structure; and   a self-formed diffusion barrier layer embedded in the sidewall surfaces of the opening of the dielectric layer, wherein the self-formed diffusion barrier layer comprises manganese atoms from the metallic seed layer which are diffused into the sidewall surfaces of the opening of the dielectric layer.   
     
     
         11 . The device of  claim 10 , wherein the metallic seed layer comprises a copper-manganese alloy, and wherein the metallic material comprises copper. 
     
     
         12 . The device of  claim 10 , wherein the manganese atoms from the metallic seed layer are diffused into the sidewall surfaces of the opening of the dielectric layer by a thermal annealing process. 
     
     
         13 . The device of  claim 10 , wherein the self-formed barrier diffusion layer comprises one of silicon manganese, manganese carbonate, and manganese oxide. 
     
     
         14 . The device of  claim 10 , further comprising a diffusion barrier layer disposed on the bottom surface of the opening in the dielectric layer. 
     
     
         15 . The device of  claim 14 , wherein the diffusion barrier layer comprises at least one of tantalum, tantalum nitride, titanium, and titanium nitride. 
     
     
         16 . The device of  claim 10 , wherein the metallic liner layer comprises cobalt, and wherein the metallic material comprises copper. 
     
     
         17 . The device of  claim 10 , wherein the dielectric layer comprises an interlayer dielectric layer of a back-end-of-line structure. 
     
     
         18 . The device of  claim 10 , wherein the opening in the dielectric layer comprises a via opening which defines a via interconnect. 
     
     
         19 . The device of  claim 10 , wherein the opening in the dielectric layer comprises a trench opening which defines a wire interconnect. 
     
     
         20 . The device of  claim 10 , wherein the opening in the dielectric layer comprises a dual damascene opening which comprises a via opening and a trench opening disposed above the via opening.