Delay locked loop circuit

Abstract

A delay locked loop circuit includes a first delay circuit that includes a plurality of first delay devices and a plurality of second delay devices, the plurality of first delay devices and the plurality of second delay devices are coupled in series with each other, a second delay circuit that includes a plurality of third delay devices equal in number and identical in configuration to the plurality of second delay devices, the plurality of third delay devices are coupled in series with each other, a phase comparator that outputs a phase difference between a first delayed clock output from the first delay circuit and a second delayed clock output from the second delay circuit, a first control circuit that outputs a first control signal that controls a time, and a second control circuit that outputs a second control signal.

What is claimed is: 
     
         1 . A delay locked loop circuit comprising:
 a first delay circuit that includes a plurality of first delay devices and a plurality of second delay devices, the plurality of first delay devices and the plurality of second delay devices are coupled in series with each other;   a second delay circuit that includes a plurality of third delay devices equal in number and identical in configuration to the plurality of second delay devices, the plurality of third delay devices are coupled in series with each other;   a phase comparator that outputs a phase difference between a first delayed clock output from the first delay circuit and a second delayed clock output from the second delay circuit;   a first control circuit that outputs a first control signal that controls a time by which the clock is delayed in each first delay device according to the phase difference; and   a second control circuit that outputs a second control signal that controls a time by which the clock is delayed in each second delay device and each third delay device.   
     
     
         2 . The delay locked loop circuit according to  claim 1 , wherein
 the first delay circuit has a configuration in which an output of the second delay device is input to the first delay device.   
     
     
         3 . The delay locked loop circuit according to  claim 2 , wherein
 the first delay circuit has a configuration in which the first delay device is sandwiched between second delay devices.   
     
     
         4 . The delay locked loop circuit according to  claim 1 , wherein
 the second control circuit performs output feedback of the second control signal by a control loop having a narrower band than a control loop in which the first control circuit performs output feedback of the first control signal.   
     
     
         5 . The delay locked loop circuit according to  claim 1 , wherein
 the second control circuit controls the second control signal according to the first control signal.   
     
     
         6 . The delay locked loop circuit according to  claim 1 , wherein
 the first delay device, the second delay device, and the third delay devices each include a first inverter, a second inverter having an output of the first inverter as an input to the second inverter, and a resistance part coupled between an output of the second inverter and an input of the first inverter,   the resistance part of the first delay device is controlled by the first control signal, and   the resistance parts of the second delay device and the third delay devices are controlled by the second control signal.   
     
     
         7 . The delay locked loop circuit according to  claim 6 , wherein
 the first delay device, the second delay device, and the third delay devices each include an even number of delay buffers coupled in series with each other, and   each of the even number of delay buffers includes the first inverter, the second inverter, and the resistance part.   
     
     
         8 . The delay locked loop circuit according to  claim 1 , wherein
 the delay locked loop circuit includes a first delay locked loop part and a second delay locked loop part each including the first delay circuit, the second delay circuit, the phase comparator, and the first control circuit,   the number of first delay devices in the first delay locked loop part is different from the number of first delay devices in the second delay locked loop part, and   the second control circuit outputs the second control signal common to the first delay locked loop part and the second delay locked loop part.   
     
     
         9 . A transmitter comprising:
 a delay locked loop circuit,   the delay locked loop circuit including
 a first delay circuit that includes a plurality of first delay devices and a plurality of second delay devices, the plurality of first delay devices and the plurality of second delay devices are coupled in series with each other, 
 a second delay circuit that includes a plurality of third delay devices equal in number and identical in configuration to the plurality of second delay devices, the plurality of third delay devices are coupled in series with each other; 
 a phase comparator that outputs a phase difference between a first delayed clock output from the first delay circuit and a second delayed clock output from the second delay circuit, 
 a first control circuit that outputs a first control signal that controls a time by which the clock is delayed in each first delay device according to the phase difference, 
 a second control circuit that outputs a second control signal that controls a time by which the clock is delayed in each second delay device and each third delay device, and 
 a first delay locked loop part and a second delay locked loop part each including the first delay circuit, the second delay circuit, the phase comparator, and the first control circuit; and 
   a pulse position modulation circuit that outputs a modulated signal based on the first control signal output from the first control circuit of the first delay locked loop part and the first control signal output from the first control circuit of the second delay locked loop part; wherein   the number of first delay devices in the first delay locked loop part being different from the number of first delay devices in the second delay locked loop part,   the second control circuit outputting the second control signal common to the first delay locked loop part and the second delay locked loop part, and   the transmitter radio-transmitting a signal based on the modulated signal.