Methods and apparatus for efficient linear combiner

Abstract

In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.

What is claimed is: 
     
         1 . An interleaved analog-to-digital converter (ADC) comprising:
 a plurality of buffers;   a plurality of analog-to-digital converters (ADC) coupled to the plurality of ADCs;   a linear combiner coupled to the plurality of ADCs; and   a clock divider, the clock divider coupled to a clock signal and the plurality of ADCs; wherein the clock divider causes the plurality of ADCs to provide an interleaved output signal to the linear combiner.   
     
     
         2 . The interleaved ADC of  claim 1  wherein the linear combiner comprises:
 an input operable to receiving the interleaved output signal; 
 a plurality of operator circuits operable to apply weighting factors to the interleaved output signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the interleaved output signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the interleaved output signal using a second sub-weight of the one of the weighting factors to provide a second tile output; 
 an adder having a first input coupled to receive the first tile output and the second tile output and providing a combined output; and 
 a scaler coupled between the input and the second operator circuit and a descaler coupled to an output of the second operator circuit. 
 
     
     
         3 . The interleaved ADC of  claim 2  in which the first sub-weight and second sub-weight are computed from bits of the one of the weighting factors. 
     
     
         4 . The interleaved ADC of  claim 2  in which the operator circuits are multipliers. 
     
     
         5 . The interleaved ADC of  claim 2  in which the first tile output is shifted upwards by a number of bits corresponding to bits in the second sub-weight. 
     
     
         6 . The interleaved ADC of  claim 2  in which the linear combiner is a filter. 
     
     
         7 . The interleaved ADC of  claim 2  in which the first operator circuit is disabled when the first sub-weight is zero. 
     
     
         8 . The interleaved ADC of claim  21  in which the one of the weighting factors is in 2's complement format and the second sub-weight is a first number of least significant bits and the first sub-weight is a second number of bits beginning with a next most significant bit after the first number of least significant bits that is rounded depending on a value of a most significant bit of the first number of least significant bits. 
     
     
         9 . The interleaved ADC of  claim 2  in which the plurality of operator circuits includes a third operator circuit in the plurality of operator circuits that performs a third operation on the signal using a third sub-weight of the one of the weighting factors. 
     
     
         10 . The interleaved ADC of  claim 2  in which the signal is quantized to a lower precision for the first operation on the signal.