Electronic device and method for fabricating the same

Abstract

An electronic device may include a semiconductor memory, and the semiconductor memory may include may include a predetermined structure; a hard mask pattern disposed over the predetermined structure and including an amorphous carbon layer; and a capping protective layer disposed on sidewalls of the hard mask pattern.

What is claimed is: 
     
         1 . An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes:
 a predetermined structure;   a hard mask pattern disposed over the predetermined structure and including an amorphous carbon layer; and   a capping protective layer disposed on sidewalls of the hard mask pattern.   
     
     
         2 . The electronic device of  claim 1 , wherein the capping protective layer includes a metal, an oxide, or a nitride, or a combination thereof. 
     
     
         3 . The electronic device of  claim 1 , wherein the capping protective layer includes Al 2 O 3 , SiO 2 , SiN, TiN, AlN, BN, Ta, W, Mo, Fe, Al, Cu, or Si, or a combination thereof. 
     
     
         4 . The electronic device of  claim 1 , wherein the capping protective layer is disposed to further cover a top surface of the hard mask pattern in addition to covering the sidewalls of the hard mask pattern. 
     
     
         5 . The electronic device of  claim 1 , wherein the predetermined structure includes a variable resistance element which includes an MTJ (Magnetic Tunnel Junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer, and
 wherein the hard mask pattern is disposed over the variable resistance element.   
     
     
         6 . The electronic device according to  claim 1 , further comprising a microprocessor which includes:
 a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor;   an operation unit configured to perform an operation based on a result that the control unit decodes the command; and   a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed,   wherein the semiconductor memory is part of the memory unit in the microprocessor.   
     
     
         7 . The electronic device according to  claim 1 , further comprising a processor which includes:
 a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data;   a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and   a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,   wherein the semiconductor memory is part of the cache memory unit in the processor.   
     
     
         8 . The electronic device according to  claim 1 , further comprising a processing system which includes:
 a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command;   an auxiliary memory device configured to store a program for decoding the command and the information;   a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and   an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,   wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system.   
     
     
         9 . The electronic device according to  claim 1 , further comprising a data storage system which includes:
 a storage device configured to store data and conserve stored data regardless of power supply;   a controller configured to control input and output of data to and from the storage device according to a command inputted from an outside;   a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and   an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,   wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system.   
     
     
         10 . The electronic device according to  claim 1 , further comprising a memory system which includes:
 a memory configured to store data and conserve stored data regardless of power supply;   a memory controller configured to control input and output of data to and from the memory according to a command inputted from an outside;   a buffer memory configured to buffer data exchanged between the memory and the outside; and   an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,   wherein the semiconductor memory is part of the memory or the buffer memory in the memory system.   
     
     
         11 . A method for fabricating an electronic device comprising a semiconductor memory, the method comprising:
 forming material layers over a substrate;   forming a hard mask pattern over the material layers, the hard mask pattern including an amorphous carbon layer;   forming a capping protective layer including a portion on sidewalls of the hard mask pattern; and   etching the material layers using the hard mask pattern as an etch barrier.   
     
     
         12 . The method of  claim 11 , wherein the capping protective layer includes a metal, an oxide, or a nitride, or a combination thereof. 
     
     
         13 . The method of  claim 11 , wherein the capping protective layer includes Al 2 O 3 , SiO 2 , SiN, TiN, AlN, BN, Ta, W, Mo, Fe, Al, Cu, or Si, or a combination thereof. 
     
     
         14 . The method of  claim 11 , wherein capping protective layer is formed to include another portion over a top surface of the hard mask pattern. 
     
     
         15 . The method of  claim 11 , wherein the forming of the capping protective layer includes performing a thermal atomic layer deposition process, a plasma chemical vapor deposition process, an ion beam deposition process, or a sputtering process. 
     
     
         16 . The method of  claim 11 , wherein the forming of the capping protective layer includes:
 forming a metal layer over the hard mask pattern and on the sidewalls of the hard mask pattern; and   subjecting the metal layer to native oxidation.   
     
     
         17 . The method of  claim 11 , wherein the forming of the capping protective layer includes:
 performing a physical etch process on the material layers and the hard mask pattern so that metals included in the material layers is redeposited on the sidewalls of the hard mask pattern.   
     
     
         18 . The method of  claim 17 , wherein the physical etch process includes an ion beam etching or a reactive ion etching, with an incident angle of ions of 0 to 30 degrees. 
     
     
         19 . The method of  claim 11 , wherein the etching of the material layers includes providing a variable resistance element which includes an MTJ (Magnetic Tunnel Junction) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction, and a tunnel barrier layer interposed between the free layer and the pinned layer, and
 wherein the hard mask pattern is disposed over the variable resistance element.   
     
     
         20 . The method of  claim 19 , wherein the forming of the material layers includes:
 forming a material layer for the free layer, a material layer for the tunnel barrier layer and a material layer for the pinned layer.