Reduction of stress in via structure

Abstract

Methods for fabricating a via structure are disclosed. In one method, fabricating the via structure includes disposing a stress buffer layer on a first surface of a substrate. The stress buffer layer has an opening aligned to a via hole of the substrate. The method further includes filling the via hole with a conductive material at least up to the first surface of the substrate. The stress buffer layer reduces stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate, and the conductive material extends into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface of the substrate around the via hole.

What is claimed is: 
     
         1 . A method for fabricating a via structure, the method comprising:
 disposing a stress buffer layer on a first surface of a substrate, the stress buffer layer having an opening aligned to a via hole of the substrate; and   filling the via hole with a conductive material at least up to the first surface of the substrate, the stress buffer layer reducing stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate;   wherein the conductive material extends into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface of the substrate around the via hole.   
     
     
         2 . The method of  claim 1 , further comprising:
 disposing a metal material on the stress buffer layer and the conductive material; and   disposing a polymer dielectric layer over the metal material to form a redistribution layer on the substrate, the redistribution layer including the stress buffer layer, the metal material and the polymer dielectric layer.   
     
     
         3 . The method of  claim 2 , further comprising forming a bump on the metal material, the bump being electrically connected with the conductive material filled in the via hole through the metal material. 
     
     
         4 . The method of  claim 1 , wherein the conductive material extends above the via hole to form a bump. 
     
     
         5 . The method of  claim 1 , wherein the substrate has a pad wiring to the via hole on the first surface and the stress buffer layer has a second opening aligned to the pad on the substrate, wherein filling the via hole further includes filling the second opening with the conductive material, and further comprising:
 disposing a polymer dielectric layer over the conductive material filled in the via hole and the stress buffer layer to form a redistribution layer on the substrate, the redistribution layer being composed of the stress buffer layer and the polymer dielectric layer; and   forming a bump on the pad of the substrate by way of the conductive material filled in the second opening, the bump being electrically connected with the conductive material filled in the via hole through the pad.   
     
     
         6 . The method of  claim 1 , wherein the substrate further includes a second surface opposite the first surface, and wherein the via hole is a through hole penetrating through the substrate from the first surface to the second surface. 
     
     
         7 . The method of  claim 8 , further comprising forming a second stress buffer layer on the second surface of the substrate, the second stress buffer layer having an opening aligned to the via hole of the substrate, wherein the conductive material extends into the opening over the second surface of the substrate and/or covers, at least in part, the edge of the second surface of the substrate around the via hole of the substrate. 
     
     
         8 . The method of  claim 1 , wherein the substrate is made of a glass or silicon, the stress buffer layer is made of polymer dielectric, and the filling comprises filling the via hole with a solder by Injection Molded Solder (IMS) technology. 
     
     
         9 . A method for fabricating a via structure, the method comprising:
 preparing a substrate having a first surface, a via hole opened to the first surface of the substrate, and a stress buffer layer disposed on the first surface of the substrate, the stress buffer layer having an opening aligned to the via hole; and   forming, in the via hole, a conductive body having a protrusion part extending into the opening of the stress buffer layer above the first surface of the substrate, the stress buffer layer reducing stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate.   
     
     
         10 . The method of  claim 9 , further comprising:
 disposing a metal material on the stress buffer layer and the conductive body; and   disposing a polymer dielectric layer over the metal material to form a redistribution layer on the substrate, the redistribution layer including the stress buffer layer, the metal material and the polymer dielectric layer.   
     
     
         11 . The method of  claim 10 , further comprising forming a bump on the metal material, the bump being electrically connected with the conductive material filled in the via hole through the metal material. 
     
     
         12 . The method of  claim 9 , wherein the substrate has a pad wiring to the via hole on the first surface and the stress buffer layer has a second opening aligned to the pad on the substrate, wherein filling the via hole further includes filling the second opening with the conductive material, and further comprising:
 disposing a polymer dielectric layer over the conductive material filled in the via hole and the stress buffer layer to form a redistribution layer on the substrate, the redistribution layer being composed of the stress buffer layer and the polymer dielectric layer; and   forming a bump on the pad of the substrate by way of the conductive material filled in the second opening, the bump being electrically connected with the conductive material filled in the via hole through the pad.   
     
     
         13 . The method of  claim 9 , wherein the substrate further includes a second surface opposite the first surface, and wherein the via hole is a through hole penetrating through the substrate from the first surface to the second surface. 
     
     
         14 . The method of  claim 14 , further comprising forming a second stress buffer layer on the second surface of the substrate, the second stress buffer layer having an opening aligned to the via hole of the substrate, wherein the conductive material extends into the opening over the second surface of the substrate and/or covers, at least in part, the edge of the second surface of the substrate around the via hole of the substrate. 
     
     
         15 . A method for fabricating a via structure, the method comprising:
 preparing a substrate having a first surface, a via hole opened to the first surface of the substrate, and a conductive material filled in the via hole; and   disposing a stress buffer layer on the first surface of the substrate and the conductive material in part, the stress buffer layer having an opening aligned to the via hole of the substrate and covering, at least in part, the edge of the first surface around the via hole of the substrate, wherein the stress buffer layers reduces stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate.   
     
     
         16 . The method of  claim 15 , further comprising:
 disposing a metal material on the stress buffer layer and the conductive material; and   disposing a polymer dielectric layer over the metal material to form a redistribution layer on the substrate, the redistribution layer including the stress buffer layer, the metal material and the polymer dielectric layer.   
     
     
         17 . The method of  claim 16 , further comprising forming a bump on the metal material, the bump being electrically connected with the conductive material filled in the via hole through the metal material. 
     
     
         18 . The method of  claim 15 , wherein the substrate has a pad wiring to the via hole on the first surface and the stress buffer layer has a second opening aligned to the pad on the substrate, wherein filling the via hole further includes filling the second opening with the conductive material, and further comprising:
 disposing a polymer dielectric layer over the conductive material filled in the via hole and the stress buffer layer to form a redistribution layer on the substrate, the redistribution layer being composed of the stress buffer layer and the polymer dielectric layer; and   forming a bump on the pad of the substrate by way of the conductive material filled in the second opening, the bump being electrically connected with the conductive material filled in the via hole through the pad.   
     
     
         19 . The method of  claim 15 , wherein the substrate further includes a second surface opposite the first surface, and wherein the via hole is a through hole penetrating through the substrate from the first surface to the second surface. 
     
     
         20 . The method of  claim 19 , further comprising forming a second stress buffer layer on the second surface of the substrate, the second stress buffer layer having an opening aligned to the via hole of the substrate, wherein the conductive material extends into the opening over the second surface of the substrate and/or covers, at least in part, the edge of the second surface of the substrate around the via hole of the substrate.