Gate-last semiconductor fabrication with negative-tone resolution enhancement

Abstract

A transistor structure includes a substrate and an active device layer formed on an upper surface of the substrate, the active device layer patterned to form multiple fins. Multiple source/drain regions are formed in the active device layer, the fins passing through the source/drain regions. The transistor structure further includes multiple source/drain contacts formed on upper surfaces of the source/drain regions, the source/drain contacts providing electrical connection to the respective source/drain regions. Multiple gate structures are formed between adjacent source/drain regions. The gate structures are electrically isolated from the active device layer by a gate dielectric layer formed between the active device layer and the respective gate structures. The gate structures are formed after formation of the source/drain regions and are self-aligned with the source/drain regions. Each of at least some of the gate structures are confined between a pair of adjacent source/drain contacts.

What is claimed is: 
     
         1 . A transistor structure, comprising:
 a substrate;   an active device layer formed on an upper surface of the substrate, the active device layer patterned to form a plurality of fins;   a plurality of source/drain regions formed in the active device layer, the plurality of fins passing through the source/drain regions;   a plurality of source/drain contacts formed on upper surfaces of the plurality of source/drain regions, the source/drain contacts providing electrical connection to the respective source/drain regions; and   a plurality of gate structures formed between adjacent source/drain regions, at least one of the gate structures being based on a configuration of a patterned trench, the gate structures being electrically isolated from the active device layer by a gate dielectric layer formed between the active device layer and the respective gate structures, the gate structures being formed subsequent to formation of the source/drain regions and being self-aligned with the source/drain regions, each of at least a subset of the plurality of gate structures being confined between a pair of adjacent source/drain contacts proximate a gate region where contact to the gate structure is formed.   
     
     
         2 . The transistor structure of  claim 1 , wherein each of at least a subset of the gate structures comprises:
 a conductive material having a prescribed work function associated therewith; and   a hard mask layer formed on an upper surface of the conductive material.   
     
     
         3 . The transistor structure of  claim 1 , wherein the substrate is a silicon-on-insulator (SOI) substrate comprising a carrier substrate, an insulating layer formed on at least a portion of an upper surface of the carrier substrate, and the active device layer formed on at least a portion of an upper surface of the insulating layer. 
     
     
         4 . The transistor structure of  claim 1 , wherein each of at least a subset of the source/drain regions comprises a Group III-V material. 
     
     
         5 . The transistor structure of  claim 4 , wherein the Group III-V material comprises at least one of indium gallium arsenide (InGaAs), gallium arsenide (GaAs) and indium phosphide (InP). 
     
     
         6 . The transistor structure of  claim 1 , wherein each of at least a subset of the plurality of gate structures is oriented in a direction substantially perpendicular to a major axis direction of the plurality of fins. 
     
     
         7 . The transistor structure of  claim 1 , wherein a vertical height of at least a subset of the plurality of fins above an upper surface of the substrate is about 30 nanometers. 
     
     
         8 . The transistor structure of  claim 1 , further comprising dielectric spacers formed on sidewalls of each of at least a subset of the plurality of source/drain contacts, each of the dielectric spacers being disposed between a corresponding one of the plurality of gate structures and an adjacent one of the source/drain contacts. 
     
     
         9 . The transistor structure of  claim 8 , further comprising a high dielectric constant (high-k) dielectric layer formed on sidewalls of at least a subset of the plurality of gate structures, the high-k dielectric layer being disposed between a corresponding one of the plurality of gate structures and an adjacent one of the dielectric spacers. 
     
     
         10 . The transistor structure of  claim 9 , wherein the high-k dielectric layer comprises at least one of hafnium oxide (HfO), zirconium oxide (ZrO), and aluminum oxide (Al 2 O 3 ). 
     
     
         11 . The transistor structure of  claim 9 , wherein the high-k dielectric layer is formed having a cross-sectional thickness of about one to three nanometers (nm). 
     
     
         12 . The transistor structure of  claim 1 , wherein the source/drain regions comprise a doped epitaxial layer covering the plurality of fins.