Monolithic co-integration of mosfet and jfet for neuromorphic/cognitive circuit applications

Abstract

Vertical MOSFET and JFET devices are incorporated on the same chip, enabling circuit designs that benefit from the simultaneous use of such devices. A fabrication method allows formation of the devices using a shared source/drain layer on a bulk semiconductor substrate.

What is claimed is: 
     
         1 . A monolithic electronic structure, comprising:
 a heavily doped source/drain layer including first and second bottom source/drain regions, the first and second bottom source/drain regions being electrically isolated from each other;   a vertical junction field-effect transistor including a doped first semiconductor channel, a heavily doped first top source/drain region, a heavily doped semiconductor gate adjoining the first semiconductor channel, and the first bottom source/drain region, the doped first semiconductor channel having a first conductivity type and the semiconductor gate having a second conductivity type opposite to the first conductivity type, and   a vertical metal-oxide-semiconductor field-effect transistor including a second semiconductor channel, a heavily doped second top source/drain region, a gate dielectric layer adjoining the first semiconductor channel, a metal gate over the gate dielectric layer, and the second bottom source/drain region, the second top source/drain region and the second bottom source/drain region having the same conductivity type as the source/drain layer.   
     
     
         2 . The monolithic electronic structure of  claim 1 , further including:
 a bulk semiconductor substrate;   a counter-doped layer between the bulk semiconductor substrate and the heavily doped source/drain layer, the counter-doped layer and the heavily doped source/drain layer having opposite conductivity types;   a shallow trench isolation region extending through the heavily doped source/drain layer and the counter-doped layer and electrically isolating the first bottom source/drain region from the second bottom source/drain region.   
     
     
         3 . The monolithic electronic structure of  claim 2 , further including:
 a bottom electrically insulating spacer adjoining the heavily doped source/drain layer, and   a top electrically insulating spacer above and parallel to the bottom electrically insulating spacer, the heavily doped semiconductor gate and the metal gate being positioned between the top and bottom electrically insulating spacers and the first and second top source/drain regions extending above the top electrically insulating spacer.   
     
     
         4 . The monolithic electronic structure of  claim 3 , wherein the first conductivity type is p-type. 
     
     
         5 . The monolithic electronic structure of  claim 3 , further including first and second semiconductor channel material extensions integral with, respectively, the first and second semiconductor channels and extending above the top electrically insulating spacer, the heavily doped first top source/drain region adjoining the first semiconductor channel material extension and the heavily doped second top source/drain region adjoining the second semiconductor channel material extension. 
     
     
         6 . The monolithic electronic structure of  claim 5 , further including first vertical spacers adjoining the heavily doped first top source/drain region and second vertical spacers adjoining the second heavily doped top source/drain region, each of the first and second vertical spacers having a bottom surface adjoining the top electrically insulating spacer. 
     
     
         7 . The monolithic electronic structure of  claim 6 , wherein the heavily doped source/drain layer consists essentially of silicon, silicon germanium, or germanium and has p-type conductivity, and further wherein the first semiconductor channel has p-type conductivity. 
     
     
         8 . The monolithic electronic structure of  claim 6 , wherein the heavily doped semiconductor gate and the metal gate both contact the bottom electrically insulating spacer. 
     
     
         9 . The monolithic electronic structure of  claim 8 , wherein the heavily doped semiconductor gate contacts the top electrically insulating spacer.