US2019213129A1PendingUtilityA1
Selective downstream cache processing for data access
Est. expiryJul 13, 2037(~11 yrs left)· nominal 20-yr term from priority
G06F 2212/1016G06F 12/0862G06F 2212/602G06F 2212/6028G06F 12/0897G06F 9/467G06F 2212/60G06F 2212/621G06F 12/0811G06F 12/0828
64
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A computer-implemented method comprising:
detecting that a data fetch request to a level 1 (L1) cache line resulted in an L1 cache miss; generating, by logic in the L1 cache and in response to detecting the L1 cache miss, a first request to access a first set of data in a level two (L2) cache; transmitting the first request to the L2 cache; predicting, by logic in the L2 cache, a location of the first set of data in the L2 cache; predicting that there will be a cache miss in the L2 cache for the first request; generating, in response to predicting that there will be a cache miss in the L2 cache for the first request, a second request to access the first set of data in a level 3 (L3) cache; generating a cancel probability score based on at least one of the workload of a cache, whether a cache line is read-only or write-only, and the exclusive or shared status of a processor; determining that the second request to the L3 cache for the first set of data will likely not be canceled based on the cancel probability score; transmitting, prior to a directory lookup indicating an actual L2 cache hit or actual L2 cache miss and in response to determining that the second request to the L3 cache for the first set of data will likely not be canceled, the second request to the L3 cache; performing a directory lookup for the first set of data in the L2 cache; determining, via the directory lookup, that there is an actual cache hit in the L2 cache for the first request; transmitting, in response to the determining that there is the actual cache hit in the L2 cache for the first request, a third request to the L3 cache to cancel the second request; clearing, by the L3 cache and in response to receiving the third request, the second request from a request buffer for the L3 cache; retrieving the first set of data from the L2 cache; receiving a fourth request for a second set of data in the L2 cache; predicting, by logic in the L2 cache, a location of the second set of data in the L2 cache; predicting that there will be a cache hit in the L2 cache for the fourth request; transmitting, in response to predicting that there will be a cache hit in the L2 cache for the fourth request, the fourth request to a request buffer for the L2 cache; determining, via a second directory lookup, that there is an actual L2 cache miss for the second set of data; sending, in response to determining that a directory indicates the actual L2 cache miss for the second set of data, the fourth request from the request buffer to a request arbiter for the L2 cache; transmitting the fourth request from the request arbiter to the L3 cache; and retrieving the second set of set of data from the L3 cache.Join the waitlist — get patent alerts
Track US2019213129A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.