Memory system and control method

Abstract

A memory system includes a nonvolatile memory a controller that controls the nonvolatile memory, and a backup power supply. In response to a detection that power from an external source to the memory system is interrupted, at which time power to the memory system starts to be supplied from the backup power supply, the controller transmits a first command to the nonvolatile memory to change a parameter for a write operation and then transmits a second command to the nonvolatile memory to carry out a write operation, such that the nonvolatile memory carries out the write operation using the changed parameter.

What is claimed is: 
     
         1 . A memory system comprising:
 a nonvolatile memory including a plurality of memory cells;   a controller configured to control the nonvolatile memory; and   a backup power supply,   wherein, in response to a detection that power from an external source to the memory system is interrupted, at which time power to the memory system starts to be supplied from the backup power supply, the controller:
 changes a mode of a write operation on first memory cells that are in an erased state, and 
 causes the nonvolatile memory to carry out the write operation having the changed mode on the first memory cells. 
   
     
     
         2 . The memory system according to  claim 1 , wherein
 the controller transmits to the nonvolatile memory a first command to change a parameter for the write operation having the changed mode.   
     
     
         3 . The memory system according to  claim 2 , wherein
 the nonvolatile memory carries out the write operation having the changed mode using the changed parameter.   
     
     
         4 . The memory system according to  claim 2 , wherein
 the parameter includes a start program voltage.   
     
     
         5 . The memory system according to  claim 2 , wherein
 the parameter includes an incremental program voltage that is added to a program voltage after completion of a program loop.   
     
     
         6 . The memory system according to  claim 2 , wherein
 the parameter includes a program voltage application time.   
     
     
         7 . The memory system according to  claim 2 , wherein
 the parameter includes a verification voltage.   
     
     
         8 . The memory system according to  claim 1 , wherein
 the nonvolatile memory carries out the write operation having the changed mode without any verification.   
     
     
         9 . The memory system according to  claim 1 , wherein
 the nonvolatile memory carries out the write operation having the changed mode without any counting of fail bits.   
     
     
         10 . The memory system according to  claim 1 , wherein
 the nonvolatile memory carries out the write operation having the changed mode in a fixed number of program loops.   
     
     
         11 . The memory system according to  claim 1 , wherein
 after the controller transmits to the nonvolatile memory a first command to carry out the write operation having a mode different from the changed mode, the controller transmits to the nonvolatile memory a second command to return a status of the write operation, and   after the controller transmits to the nonvolatile memory the first command to carry out the write operation having the changed mode, the controller does not transmit the second command to the nonvolatile memory.   
     
     
         12 . The memory system according to  claim 1 , wherein
 the write operation performed on the first memory cells and having a mode different from the changed mode takes a first completion time, and   the write operation performed on the first memory cells and having the changed mode takes a second completion time that is shorter than the first completion time.   
     
     
         13 . A method of controlling a nonvolatile memory including a plurality of memory cells, the method comprising:
 in response to a detection that power from an external source to the nonvolatile memory is interrupted,
 changing a mode of a write operation on first memory cells that are in an erased state, and 
 causing the nonvolatile memory to carry out the write operation having the charged mode on the first memory cells. 
   
     
     
         14 . The method according to  claim 13 , wherein
 a first command is transmitted to the nonvolatile memory to change a parameter for the write operation having the changed mode.   
     
     
         15 . The method according to  claim 14 , wherein
 the nonvolatile memory carries out the write operation having the changed mode using the changed parameter.   
     
     
         16 . The method according to  claim 14 , wherein
 the parameter includes a start program voltage.   
     
     
         17 . The method according to  claim 14 , wherein
 the parameter includes an incremental program voltage that is added to a program voltage after completion of a program loop.   
     
     
         18 . The method according to  claim 14 , wherein
 the parameter includes a program voltage application time.   
     
     
         19 . The method according to  claim 14 , wherein
 the parameter includes a verification voltage.   
     
     
         20 . The method according to  claim 13 , further comprising:
 after transmitting to the nonvolatile memory a first command to carryout the write operation having a mode different from the changed mode, transmitting to the nonvolatile memory a second command to return a status of the write operation, wherein   after the first command is transmitted to the nonvolatile memory to carry out the write operation having the changed mode, the second command is not transmitted to the nonvo