PROCESS FOR NiFe FLUXGATE DEVICE

Abstract

An etchant for simultaneously etching NiFe and AlN with approximately equal etch rates that comprises phosphoric acid, acetic acid, nitric acid and deionized water. Alternating layers of NiFe and AlN may be used to form a magnetic core of a fluxgate magnetometer in an integrated circuit. The wet etch provides a good etch rate of the alternating layers with good dimensional control and with a good resulting magnetic core profile. The alternating layers of NiFe and AlN may be encapsulated with a stress relief layer. A resist pattern may be used to define the magnetic core geometry. The overetch time of the wet etch may be controlled so that the magnetic core pattern extends at least 1.5 um beyond the base of the magnetic core post etch. The photo mask used to form the resist pattern may also be used to form a stress relief etch pattern.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a first dielectric layer on a semiconductor wafer;   an etch stop layer on the first dielectric layer;   a first stress relief layer on the etch stop layer;   a magnetic core composed of alternating layers of NiFe permalloy and AlN dielectric on the first stress relief layer; and   a second stress relief layer on the first stress relief layer and on the top and sides of the magnetic core, wherein the first and second stress relief layers extend laterally beyond the magnetic core.   
     
     
         2 . The integrated circuit of  claim 1 , wherein the first stress relief has a thickness of between 30 nm and 50nm and where the second stress relief layer has a thickness between 90 nm and 300 nm. 
     
     
         3 . The integrated circuit of  claim 1 , wherein each layer of NiFe permalloy has a thickness between 225 nm and 425 nm and where each layer of AlN has a thickness between 5 nm and 15 nm and where there are between 3 and 10 layers each of NiFe permalloy and AlN. 
     
     
         4 . The integrated circuit of  claim 1 , wherein the first and second stress relief layers are selected from the group consisting of Ti, TiN, Ta, TaN, Ru, and Pt. 
     
     
         5 . The integrated circuit of  claim 1 , wherein the first stress relief layer is titanium with a thickness between 30 nm and 50 nm and wherein the second stress relief layer is titanium with a thickness between 90 nm and 300 nm. 
     
     
         6 . The integrated circuit of  claim 1 , wherein the etch stop layer is silicon nitride with a thickness between 35 nm and 150 nm. 
     
     
         7 . The integrated circuit of  claim 1 , wherein the first and second stress relief layers extend laterally beyond the magnetic core by at least 1.5 μm. 
     
     
         8 . An integrated circuit, comprising:
 a first dielectric layer on a semiconductor wafer;   a silicon nitride layer on the first dielectric layer;   a first titanium layer on the silicon nitride layer;   a magnetic core composed of alternating layers of NiFe permalloy and AlN dielectric on the first titanium layer; and   a second titanium layer on the first titanium layer and on the top and sides of the magnetic core, wherein the first and second titanium layers extend laterally beyond the magnetic core.   
     
     
         9 . The integrated circuit of  claim 8 , wherein the silicon nitride layer has a thickness between 35 nm and 150 nm. 
     
     
         10 . The integrated circuit of  claim 8 , wherein the first titanium layer has a thickness of between 30 nm and 50 nm and where the second titanium layer has a thickness between 90 nm and 300 nm. 
     
     
         11 . The integrated circuit of  claim 8 , wherein each layer of NiFe permalloy has a thickness between 225 nm and 425 nm and where each layer of AlN has a thickness between 5 nm and 15 nm and where there are between 3 and 10 layers each of NiFe permalloy and AlN in the magnetic core. 
     
     
         12 . The integrated circuit of  claim 8 , wherein the first and second titanium layers extend laterally beyond the magnetic core by at least 1.5 μm. 
     
     
         13 . An integrated circuit, comprising:
 a first dielectric layer over a semiconductor wafer;   a silicon nitride layer in direct contact with the first dielectric layer;   a first titanium layer in direct contact with the silicon nitride layer;   a magnetic core composed of alternating layers of NiFe permalloy and AlN dielectric on the first titanium layer; and   a second titanium layer in direct contact with the first titanium layer and with the top and sides of the magnetic core, wherein the first and second titanium layers extend laterally beyond the magnetic core.   
     
     
         14 . The integrated circuit of  claim 13 , wherein the silicon nitride layer has a thickness between 35 nm and 150 nm. 
     
     
         15 . The integrated circuit of  claim 13 , wherein the first titanium layer has a thickness of between 30 nm and 50 nm and where the second titanium layer has a thickness between 90 nm and 300 nm. 
     
     
         16 . The integrated circuit of  claim 13 , wherein each layer of NiFe permalloy has a thickness between 225 nm and 425 nm and where each layer of AlN has a thickness between 5 nm and 15 nm and where there are between 3 and 10 layers each of NiFe permalloy and AlN in the magnetic core. 
     
     
         17 . The integrated circuit of  claim 13 , wherein the first and second titanium layers extend laterally beyond the magnetic core by at least 1.5 μm.