US2019207032A1PendingUtilityA1

Semiconductor device

Assignee: SHARP KKPriority: Oct 8, 2014Filed: Mar 6, 2019Published: Jul 4, 2019
Est. expiryOct 8, 2034(~8.2 yrs left)· nominal 20-yr term from priority
H01L 27/1225H01L 29/7869H01L 29/78696C23C 14/3464C23C 14/5873C23C 14/08H01L 29/78618H01L 29/786C23C 16/42H10D 30/6757H10D 99/00H10D 86/451H10D 86/423H10D 86/60H10D 30/6713H10D 30/67H10D 30/6755
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Claims

Abstract

In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).

Claims

exact text as granted — not AI-modified
1 . A semiconductor device comprising:
 a plurality of layers being stacked to define a thin film transistor, and including a semiconductor layer made of an oxide semiconductor; wherein   in the semiconductor layer, a proportion of pure zinc indicating a ratio of pure zinc to all components of the oxide semiconductor is higher at an interface of the semiconductor layer to an upper layer than in a bulk.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the proportion of pure zinc at a peripheral edge portion, of a pattern of the semiconductor layer, of the interface is higher than the proportion of pure zinc in the bulk. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the proportion of pure zinc at an upper surface portion, of a pattern of the semiconductor layer, of the interface is higher than the proportion of pure zinc in the bulk. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein both the proportion of pure zinc at a peripheral edge portion, of a pattern of the semiconductor layer, of the interface and the proportion of pure zinc at an upper surface portion, of the pattern of the semiconductor layer, of the interface are higher than the proportion of pure zinc in the bulk. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein, in the semiconductor layer, a proportion of pure indium indicating a ratio of pure indium to all components of the oxide semiconductor is higher at an interface of the semiconductor layer to an upper layer than in the bulk. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein the upper layer of the semiconductor layer is defined by a passivation film to protect the semiconductor layer. 
     
     
         7 . The semiconductor device according to  claim 1 , wherein the upper layer of the semiconductor layer is an insulating film to insulate a gate electrode of the thin film transistor and the semiconductor layer from each other. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein the upper layer of the semiconductor layer is defined by a silicon dioxide film. 
     
     
         9 . The semiconductor device according to  claim 1 , wherein the oxide semiconductor is indium gallium zinc oxide. 
     
     
         10 . The semiconductor device according to  claim 9 , wherein the indium gallium zinc oxide is crystalline.

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