Semiconductor device

Abstract

A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the cod is 7 μm or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 μm or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view. Even if such wirings (linear wiring parts) are arranged under the coil, the characteristics (for example, RF characteristics) of the semiconductor device are not deteriorated. In addition, the area of the semiconductor device can be reduced or high integration of elements can be realized by laminating elements (for example, MOM capacitance elements and the like) having the coil and the linear wiring parts.

1 . A semiconductor device comprising:
 a substrate;   a first wiring formed above the substrate; and   a coil formed above the first wiring,   wherein the first wiring has a plurality of linear wiring parts,   wherein a distance between the upper face of the first wiring and the bottom face of the coil is 7 μm or larger, and   wherein the linear wiring parts do not configure a loop wiring.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein each of the plurality of linear wiring parts has a width of 1 μm or smaller,   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein the first wiring configures a capacitance.   
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the capacitance has a first electrode and a second electrode.   
     
     
         5 . The semiconductor device according to  claim 4 ,
 wherein the first electrode and the second electrode are formed in a comb-like shape.   
     
     
         6 . The semiconductor device according to  claim 5 ,
 further comprising a first insulation film formed between the substrate and the first wiring,   wherein a transistor having a first gate electrode formed in the first insulation film is provided.   
     
     
         7 . The semiconductor device according to  claim 6 ,
 wherein a varactor having a second gate electrode formed in the first insulation film is provided.   
     
     
         8 . The semiconductor device according to  claim 7 ,
 wherein the coil, the transistor, and the varactor configure an oscillation circuit.   
     
     
         9 . The semiconductor device according to  claim 8 ,
 wherein the capacitance and the oscillation circuit configure a PLL.   
     
     
         10 . The semiconductor device according to  claim 1 ,
 wherein the coil is provided in a re-wiring layer.   
     
     
         11 . A semiconductor device comprising:
 a substrate;   an element formed above the substrate;   a first wiring formed above the element;   a coil formed above the first wiring,   wherein the first wiring has a plurality of linear first wiring parts,   wherein a distance between the upper face of the first wiring and the bottom face of the coil is 7μm or larger, and   wherein the linear first wiring parts do not configure a loop wiring.   
     
     
         12 . A semiconductor device according to  claim 11 :
 wherein each of the plurality of linear first wiring parts has a wiring width of 1 μm or smaller.   
     
     
         13 . The semiconductor device according to  claim 11 ,
 wherein the first wiring configures a capacitance.   
     
     
         14 . The semiconductor device according to  claim 13 ,
 wherein the capacitance has a first electrode and a second electrode.   
     
     
         15 . The semiconductor device according to  claim 14 ,
 wherein the first electrode and the second electrode are formed in a comb-like shape.   
     
     
         16 . The semiconductor device according to  claim 15 ,
 wherein the element is a transistor, and   wherein a plurality of first gate electrodes formed over the substrate through a first gate insulation film, a plurality of diffusion layers formed in the substrate on both sides of each of the first gate electrodes, and a plurality of linear second wiring parts coupled to the diffusion layers are provided.   
     
     
         17 . The semiconductor device according to  claim 16 ,
 wherein another element is provided,   wherein the another element is a varactor, and   wherein a plurality of second gate electrodes formed over the substrate through a second gate insulation film, a plurality of diffusion layers formed in the substrate on both sides of each of the second gate electrodes, and a plurality of linear third wiring parts coupled to the diffusion layers are provided.   
     
     
         18 . The semiconductor device according to  claim 17 ,
 wherein the coil, the transistor, and the varactor configure an oscillation circuit.   
     
     
         19 . The semiconductor device according to  claim 18 ,
 wherein the capacitance and the oscillation circuit configure a PLL.   
     
     
         20 . The semiconductor device according to  claim 11 ,
 wherein the coil is provided in a re-wiring layer.