US2019206752A1PendingUtilityA1

Integrated circuit packages with cavities and methods of manufacturing the same

Assignee: TEXAS INSTRUMENTS INCPriority: Dec 29, 2017Filed: Dec 29, 2017Published: Jul 4, 2019
Est. expiryDec 29, 2037(~11.4 yrs left)· nominal 20-yr term from priority
H10W 90/734H10W 90/732H10W 72/884H10W 90/811H10W 74/114H10W 74/016H10W 72/50H10W 70/635H10W 70/479H10W 70/458H10W 70/415H10W 70/041H10W 74/00H10W 72/072H10W 72/075H10W 74/15H10W 72/877H10W 72/879H10W 72/865H10W 72/859H10W 90/756H10W 72/547H10W 72/07554H10W 90/752H10W 90/00H10W 72/073H10W 72/07236H10W 72/354H10W 72/247H10W 72/07254H10W 90/722H10W 90/736H10W 72/347H10W 72/07354H10W 70/417H10W 74/111H10W 74/121H10W 74/124H01L 23/3121H01L 24/49H01L 23/49586H01L 21/4825H01L 24/73H01L 23/49827H01L 23/49861H01L 2224/32225H01L 23/4951H01L 23/315H10H 20/857H10H 20/854
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Claims

Abstract

Integrated circuit packaging with cavities and methods of manufacturing the same are disclosed. An example apparatus includes a semiconductor die and a housing enclosing portions of the semiconductor die. The housing defines an opening that extends from a surface of the semiconductor die to an external environment, the housing formed of a first material. The example apparatus includes a second material disposed within the opening to block exposure of the semiconductor die to the external environment.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An apparatus, comprising:
 a semiconductor die;   a housing enclosing portions of the semiconductor die, the housing defining an opening that extends from a surface of the semiconductor die to an external environment, the housing formed of a first material; and   a second material disposed within the opening to block exposure of the semiconductor die to the external environment.   
     
     
         2 . The apparatus of  claim 1 , wherein the semiconductor die is a first semiconductor die, the apparatus further including a second semiconductor die mounted to the portion of the first semiconductor die, the second material covering portions of the second semiconductor die. 
     
     
         3 . The apparatus of  claim 2 , wherein the first material has a first modulus of elasticity and the second material has a second modulus of elasticity, the first modulus of elasticity being greater than the second modulus of elasticity. 
     
     
         4 . The apparatus of  claim 3 , wherein the second semiconductor die includes a stress-sensitive semiconductor device. 
     
     
         5 . The apparatus of  claim 2 , wherein the second material allows light to pass therethrough. 
     
     
         6 . The apparatus of  claim 5 , wherein the second semiconductor die includes an optical semiconductor device. 
     
     
         7 . The apparatus of  claim 2 , wherein the second semiconductor die is wire bonded to the portion of the first semiconductor die. 
     
     
         8 . The apparatus of  claim 1 , wherein the semiconductor die is mounted to a leadframe within the housing. 
     
     
         9 . An integrated circuit package, comprising:
 a substrate;   a first die attached to and electrically connected to the substrate;   a second die attached to and electrically connected to the first die;   a first material covering portions of the first die; and   a second material covering portions of the second die and portions of a surface of the first die, the second material within a cavity of the first material.   
     
     
         10 . The integrated circuit packaging of  claim 9 , wherein the first material has different light transmission properties than the second material. 
     
     
         11 . The integrated circuit packaging of  claim 10 , wherein the second die includes a stress-sensitive semiconductor device. 
     
     
         12 . The integrated circuit packaging of  claim 11 , wherein the first material has a first modulus of elasticity and the second material has a second modulus of elasticity, the first modulus of elasticity being greater than the second modulus of elasticity. 
     
     
         13 . The integrated circuit packaging of  claim 10 , wherein the second die corresponds to an optical semiconductor device. 
     
     
         14 . The integrated circuit packaging of  claim 13 , wherein the second material is at least one of transparent or translucent. 
     
     
         15 . A method, comprising:
 forming an opening in a housing enclosing a die, the opening to expose a surface of the die to an external environment, the housing formed of a first material; and   applying a second material within the opening to isolate the surface of the die from the external environment.   
     
     
         16 . The method of  claim 15 , further including forming the opening in the housing by:
 enclosing the die in a mold assembly, the mold assembly including a pin to define the opening;   injecting the first material into the mold assembly and around the pin; and   removing the mold assembly.   
     
     
         17 . The method of  claim 15 , further including forming the opening in the housing by:
 applying a removable material to the surface of the die;   molding the first material around the die and the removable material; and   removing the removable material.   
     
     
         18 . The method of  claim 15 , wherein the die is a first die, the method further including:
 mounting a second die to the surface of the first die; and   applying the second material after mounting the second die, the second material encapsulating the second die.   
     
     
         19 . The method of  claim 18 , wherein the second die includes a stress-sensitive semiconductor device, the second material has a modulus of elasticity that is lower than the first material so that stress on the second die is less than stress on the first die. 
     
     
         20 . The method of  claim 18 , wherein the second die corresponds to an optical semiconductor device, the second material is at least one of transparent or translucent to enable light to pass between the second die and the external environment.

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