US2019199294A1PendingUtilityA1
Methods for thermal management in amplifiers
Est. expiryOct 22, 2035(~9.2 yrs left)· nominal 20-yr term from priority
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Claims
Abstract
Methods of managing heat generated by amplifiers are disclosed. A metal pillar, a plurality of resistors, and a transistor array are formed over a silicon substrate. The plurality of resistors provide emitter-ballasting for the amplifier. A footprint defined by a periphery of the metal pillar is adjacent to a footprint defined by a periphery of the transistor array and overlaps a footprint defined by a periphery of the plurality of resistors so that heat generated during operation of the amplifier is transferred through the silicon substrate to the metal pillar.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A method for thermal management of an amplifier, the method comprising:
forming a transistor array over a silicon substrate; and forming a metal pillar over the silicon substrate such that a footprint defined by a periphery of the metal pillar is adjacent to a footprint defined by a periphery of the transistor array, heat generated during operation of the transistor array being transferred through the silicon substrate to the metal pillar.
2 . The method of claim 1 wherein the footprint defined by the periphery of the metal pillar further overlaps a footprint defined by a periphery of a plurality of first resistors formed over the silicon substrate.
3 . The method of claim 2 wherein a first end of a resistor of the plurality of first resistors is in communication with an emitter of a transistor of the transistor array.
4 . The method of claim 3 wherein the resistor of the plurality of first resistors provides emitter-ballasting for the amplifier.
5 . The method of claim 3 wherein a second end of the resistor of the plurality of first resistors in communication with the metal pillar.
6 . The method of claim 1 wherein the metal pillar is configured to provide a flip chip interconnection for the amplifier.
7 . The method of claim 1 wherein the metal pillar is configured to provide a ground connection.
8 . The method of claim 1 further comprising forming one or more inter-level metal layers between the silicon substrate and the metal pillar.
9 . The method of claim 8 wherein the heat is transferred through the one or more inter-level metal layers before reaching the metal pillar.
10 . The method of claim 1 wherein the transistor array includes an NPN bipolar transistor.
11 . The method of claim 1 wherein the transistor array includes at least a portion of a silicon germanium power amplifier.
12 . A method for thermal management of a flip chip implementation of an amplifier, the method comprising:
forming a transistor array and a plurality of first resistors over a silicon substrate, a first end of a resistor of the plurality of first resistors in communication with an emitter of a transistor of the transistor array; and forming a metal pillar over the silicon substrate such that a footprint defined by a periphery of the metal pillar is adjacent to a footprint defined by a periphery of the transistor array and overlaps a footprint defined by a periphery of the plurality of first resistors, a second end of the resistor of the plurality of first resistors in communication with the metal pillar, heat generated during operation of the transistor of the transistor array being transferred through the silicon substrate to the metal pillar.
13 . The method of claim 12 wherein the metal pillar is configured to provide a flip chip interconnection for the amplifier.
14 . The method of claim 12 wherein the metal pillar is configured to provide a ground connection.
15 . The method of claim 12 wherein the resistor of the plurality of first resistors providing emitter-ballasting for the amplifier.
16 . The method of claim 12 further comprising forming a second plurality of resistors, a resistor of the second plurality of resistors in communication with a base of the transistor.
17 . The method of claim 16 wherein the resistor of the second plurality of resistors providing base-ballasting for the amplifier.
18 . The method of claim 12 further comprising forming one or more inter-level metal layers between the silicon substrate and the metal pillar.
19 . The method of claim 12 wherein the transistor array includes an NPN bipolar transistor.
20 . The method of claim 12 wherein the transistor array includes at least a portion of a silicon germanium power amplifier.Join the waitlist — get patent alerts
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