Semiconductor Devices and Methods of Manufacturing the Same

Abstract

Semiconductor devices and methods of fabricating the same are provided. The method includes forming on a substrate an active pattern that protrudes from the substrate and extends in one direction; forming on the active pattern a sacrificial gate structure that extends in a direction intersecting the active pattern; forming on a side surface of the sacrificial gate structure a first spacer including a first portion at a lower level than a top surface of the active pattern and a second portion on the first portion, and reducing a thickness of the second portion of the first spacer.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 forming an active pattern on a substrate, the active pattern protruding from the substrate and extending in a first direction;   forming a sacrificial gate structure on the active pattern, the sacrificial gate structure extending in a second direction and the second direction intersecting the first direction of the active pattern;   forming a first spacer on a side surface of the sacrificial gate structure, the first spacer including a first portion and a second portion, the first portion having a surface at a lower level than an upper surface of the active pattern and the second portion being on the first portion; and   decreasing a thickness of the second portion of the first spacer.   
     
     
         2 . The method of  claim 1 , wherein decreasing the thickness of the second portion of the first spacer comprises:
 forming a first mask on the first portion of the first spacer and exposing the second portion of the first spacer, the first mask having a top surface at a same level as or a lower level than the top surface of the active pattern;   performing a first etching process on the second portion according to the first mask; and   removing the first mask.   
     
     
         3 . The method of  claim 1 :
 wherein, after the thickness of the second portion is decreased, the first portion and the second portion have a stepped shape on a boundary therebetween; and   wherein the thickness of the second portion is less than a thickness of the first portion.   
     
     
         4 . The method of  claim 1 , further comprising, wherein after decreasing the thickness of the second portion of the first spacer is followed by forming a second spacer on the first portion, the second spacer covering the sacrificial gate structure. 
     
     
         5 . The method of  claim 4 , wherein forming the second spacer comprises:
 forming a second mask on the first portion of the first spacer, the second mask having a top surface at a same level as or a lower level than the top surface of the active pattern;   forming a spacer layer covering the second mask and the sacrificial gate structure;   forming a second spacer by removing the spacer layer on the second mask; and   removing the second mask.   
     
     
         6 . The method of  claim 4 , wherein a dielectric constant of the second spacer is less than a dielectric constant of the first spacer. 
     
     
         7 . The method of  claim 4 , wherein, on a boundary between the first portion and the second portion, a sum of a thickness of the second spacer and the thickness of the second portion is less than a thickness of the first portion. 
     
     
         8 . The method of  claim 4 , wherein forming the second spacer is performed after performing a second etching process to remove the second portion. 
     
     
         9 . The method of  claim 8 , wherein the second spacer is formed at a higher level than the upper surface of the active pattern, the second spacer being in contact with the sacrificial gate structure. 
     
     
         10 . The method of  claim 1 , wherein the active pattern comprises:
 a first semiconductor pattern and a second semiconductor pattern that are sequentially stacked on the substrate;   a first sacrificial layer between the substrate and the first semiconductor pattern; and   a second sacrificial layer between the first semiconductor pattern and the second semiconductor pattern.   
     
     
         11 . The method of  claim 1 , further comprising:
 forming recess regions by etching the active pattern using the first spacer as an etching mask; and   forming source/drain patterns filling the recess regions,   wherein a sidewall of the recess region protrudes toward and below the sacrificial gate structure.   
     
     
         12 . A semiconductor device, comprising:
 a substrate having an active region; and   a transistor on the active region of the substrate,   wherein the transistor comprises:
 a channel pattern extending in a first direction on the substrate; 
 a gate electrode crossing over the channel pattern in a second direction; 
 a dielectric layer between the channel pattern and the gate electrode; and 
 a first spacer covering a side surface of the gate electrode, 
   wherein the first spacer comprises a first portion at a lower level than a top surface of the channel pattern and a second portion on the first portion; and   wherein a thickness of the second portion is less than a thickness of the first portion.   
     
     
         13 . The device of  claim 12 , further comprising a second spacer on the first portion and covering the second portion. 
     
     
         14 . The device of  claim 13 , wherein a dielectric constant of the second spacer is less than a dielectric constant of the first spacer. 
     
     
         15 . The device of  claim 13 , wherein, on a boundary between the first portion and the second portion, a sum of a thickness of the second spacer and the thickness of the second portion is less than the thickness of the first portion. 
     
     
         16 . The device of  claim 12 :
 wherein an active pattern comprises semiconductor patterns sequentially stacked on the substrate; and   wherein the gate electrode comprises a first metal pattern between the semiconductor patterns and a second metal pattern on the first metal pattern, the first metal pattern filling a gap between the semiconductor patterns.   
     
     
         17 . A semiconductor device, comprising:
 an active pattern protruding from a substrate and extending in a first direction;   a gate electrode running across the active pattern in a second direction;   a first spacer on a side surface of the gate electrode and disposed at a lower level than a top surface of the active pattern; and   a second spacer on the side surface of the gate electrode and on the first spacer,   wherein a dielectric constant of the second spacer is less than a dielectric constant of the first spacer.   
     
     
         18 . The device of  claim 17 , wherein a portion of the first spacer extends between the gate electrode and the second spacer. 
     
     
         19 . The device of  claim 17 , wherein a side surface of the first spacer is coplanar with a side surface of the second spacer. 
     
     
         20 . The device of  claim 17 :
 wherein the active pattern comprises semiconductor patterns sequentially stacked on the substrate; and   wherein the gate electrode comprises a first metal pattern between the semiconductor patterns and a second metal pattern on the first metal pattern, the first metal pattern filling a gap between the semiconductor patterns.