Method of fabrication of a semiconductor device including one or more nanostructures

Abstract

A method of fabrication of a semiconductor device including the implementation of the following steps: fabrication of a stack including at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, such that the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure intended to be made; and thermal treatment of the stack at a temperature which causes surface migration of atoms of the second semiconductor of the second portion towards at least one part of the first portion which exhibits at least one free surface and at which the nanostructure containing at least atoms of the second semiconductor is formed.

1 . A method of fabrication of a semiconductor device, the method comprising:
 fabricating at least one stack comprising at least one first portion of a first semiconductor and at least one second portion of a second semiconductor which is different from the first semiconductor, such that the thickness of at least the first portion is substantially equal to the thickness of at least one nanostructure intended to be made; and   thermally treating the stack at a temperature which causes at least one surface migration of atoms of the second semiconductor of the second portion towards at least one part of the first portion which exhibits at least one free surface and at and/or within which the nanostructure comprising at least atoms of the second semiconductor is formed.   
     
     
         2 . The method according to  claim 1 , wherein:
 the first semiconductor comprises Si, and/or   the second semiconductor comprises Ge, and/or   the thermal treatment temperature is between about 750° C. and 850° C., and/or   the thermal treatment is carried out in an atmosphere containing hydrogen.   
     
     
         3 . The method according to  claim 2 , wherein the second semiconductor comprises SiGe which has a germanium concentration between about 20% and 80%. 
     
     
         4 . The method according to  claim 1 , wherein the thickness of the first portion is between about 4 nm and 20 nm. 
     
     
         5 . The method according to  claim 1 , wherein the stack comprises several alternating first and second portions, and wherein the implementation of the thermal treatment causes at least one surface migration of atoms of the second semiconductor from the second portions towards parts of the first portions which each exhibit at least one free surface and at each of which at least one nanostructure comprising at least atoms of the second semiconductor is formed. 
     
     
         6 . The method according to  claim 5 , wherein several second portions comprise second semiconductors with different atomic compositions and/or different concentrations from one to another, forming nanostructures which comprise different semiconductors. 
     
     
         7 . The method according to  claim 6 , wherein each second portion may comprise SiGe which has a concentration of germanium which is different from that of the SiGe of other second portions. 
     
     
         8 . The method according to  claim 5 , wherein several of the first portions comprise different thicknesses from one to another, and/or several of the second portions comprise different thicknesses from one to another. 
     
     
         9 . The method according to  claim 1 , wherein:
 the stack is made on a substrate and   the second semiconductor is capable of being selectively etched relative to the first semiconductor,   wherein the method further comprises, between the fabrication of the stack and the thermal treatment of the stack:   fabricating, on a part of the stack, external spacers and at least one dummy gate arranged between the external spacers,   etching the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires, and   wherein said at least one part of the first portion corresponds to extremities of the remaining part of the first portion,   where the method further comprises, after the implementation of the thermal treatment forming nanostructures at the extremities of the remaining part of the first portion:   fabricating source and drain regions by epitaxy of semiconductor from at least the nanostructures, and such that the second semiconductor is capable of being selectively etched relative to the semiconductor of the source and drain regions,   removing the dummy gate and the remaining part of the second portion, and   fabricating a gate between the external spacers and surrounding a channel of the semiconductor device formed by the remaining part of the first portion.   
     
     
         10 . The method according to  claim 9 , wherein the semiconductor of the source and drain region is doped silicon. 
     
     
         11 . The method according to  claim 9 , further comprising between the stack etching and the source and drain regions fabrication:
 partial etching of the remaining part of the second portion from the extremities of the remaining part of the second portion revealed by the etching of the stack, forming cavities arranged at least beneath the external spacers, and   fabricating, internal spacers within the cavities.   
     
     
         12 . The method according to  claim 9 , further comprising, between the thermal treatment and the making of the source and drain regions:
 removing the nanostructures, where the source and drain regions are made by epitaxy of semiconductor from at least the remaining portion of the first portion.   
     
     
         13 . The method according to  claim 9 , further comprising,
 between the making of the source and drain regions and the removing of the dummy gate and the remaining part of the second portion:   doping the semiconductor of source and drain regions, then annealing which diffuses dopants into the semiconductor of the source and drain regions, or   making the source and drain regions such that the semiconductor of the source and drain regions is doped.   
     
     
         14 . The method according to  claim 1 , wherein:
 the stack is made on a substrate and   the first semiconductor is capable of being selectively etched relative to the second semiconductor,   wherein the method further comprises, between the fabrication of the stack and the thermal treatment of the stack:   fabricating on a part of the stack external spacers and at least one dummy gate arranged between the external spacers, and   etching the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires,   wherein said at least one part of the first portion corresponds to the extremities of the remaining part of the first portion and the nanostructures form etch stop elements intended to protect the semiconductor of the source and drain regions,   wherein the method further comprises, after implementation of the thermal treatment forming nanostructures at the extremities of the remaining part of the first portion:   fabricating source and drain regions by epitaxy of semiconductor from at least the nanostructures and the remaining part of the second portion,   removing the dummy gate and the remaining part of the first portion, and   fabricating a gate between the external spacers and surrounding a channel of the semiconductor device formed by the remaining part of the second portion.   
     
     
         15 . The method according to  claim 1 , wherein:
 the stack is made on a substrate and   the second semiconductor is capable of being selectively etched relative to the first semiconductor,   wherein the method further comprises, between the fabrication of the stack and the thermal treatment of the stack:   fabricating on a part of the stack of external spacers and at least one dummy gate arranged between the external spacers,   etching the stack such that the remaining parts of the first and second portions are arranged beneath the dummy gate and beneath the external spacers and form a stack of nanowires,   removing the dummy gate, and   etching at least one region of the remaining part of the second portion not covered by the external spacers,   wherein said at least one part of the first portion corresponds to a region of the remaining part of the first portion not covered by external spacers,   wherein the method further comprises, after the thermal treatment has been carried out:   fabricating a gate between the external spacers covering the nanostructure,   etching the remaining part of the second portion,   fabricating internal spacers beneath the external spacers and in the locations formed by etching of the remaining part of the second portion, and   fabricating source and drain regions by epitaxy of semiconductor from at least the remaining part of the first portion.