Semiconductor memory structure and method for preparing the same

Abstract

The present disclosure provides a semiconductor memory structure including a substrate, a plurality of first trenches disposed in the substrate, a plurality of second trenches disposed in the substrate and spaced apart from the first trenches, a plurality of buried digit lines disposed in the first trenches, and a plurality of buried word lines disposed in the second trenches. The first trenches include a first depth, and the second trenches include a second depth. The second depth of the second trenches is greater than the first depth of the first trenches. Top surfaces of the buried word lines are lower than bottom surfaces of the buried digit lines.

1 . A semiconductor memory structure comprising:
 a substrate;   a plurality of first trenches disposed in the substrate, the first trenches comprising a first depth;   a plurality of second trenches disposed in the substrate and spaced apart from the first trenches, wherein the second trenches comprises a second depth greater than the first depth;   a plurality of buried digit lines disposed in the first trenches; and   a plurality of buried word lines disposed in the second trenches,   wherein top surfaces of the buried digit lines are lower than bottom surfaces of the buried word lines.   
     
     
         2 . The semiconductor memory structure of  claim 1 , wherein the first trenches and the second trenches are alternately arranged. 
     
     
         3 . The semiconductor memory structure of  claim 1 , further comprising a plurality of first isolation structures individually disposed on the buried digit lines in the first trenches. 
     
     
         4 . The semiconductor memory structure of  claim 1 , further comprising a plurality of second isolation structures disposed in the second trenches, wherein the buried word lines are spaced apart from the substrate by the second isolation structures. 
     
     
         5 . The semiconductor memory structure of  claim 1 , further comprising a plurality of first doped regions individually disposed in the substrate under the first trenches. 
     
     
         6 . The semiconductor memory structure of  claim 4 , wherein each first doped region surrounds a sidewall and a bottom of a buried digit line. 
     
     
         7 . The semiconductor memory structure of  claim 1 , further comprising a plurality of second doped regions disposed in the substrate between the first trenches and the second trenches. 
     
     
         8 . The semiconductor memory structure of  claim 7 , further comprising a plurality of capacitors individually electrically connected to the second doped regions. 
     
     
         9 . The semiconductor memory structure of  claim 1 , wherein each of the buried word lines comprises a curved surface curving toward the first trenches. 
     
     
         10 . The semiconductor memory structure of  claim 1 , further comprising a plurality of third isolation structures disposed in the substrate, wherein the third isolation structures comprises a third depth. 
     
     
         11 . The semiconductor memory structure of  claim 10 , wherein the first depth of the first trenches and the second depth of the second trenches are less than the third depth of the third isolation structures. 
     
     
         12 . A method for preparing a semiconductor memory structure, comprising:
 providing a substrate comprising a plurality of active regions extending in a first direction;   forming a plurality of first trenches in the substrate, the first trenches comprising a first depth and extending in a second direction different from the first direction;   forming a plurality of buried digit lines in the first trenches;   forming a plurality of second trenches in the substrate, the second trenches comprising a second depth and extending in a third direction different from the first direction and the second direction;   deepening portions of the second trenches to form a plurality of third trenches in the substrate, the third trenches comprising a third depth; and   forming a plurality of buried word lines in the third trenches.   
     
     
         13 . The method of  claim 12 , wherein the substrate further comprises a plurality of first isolation structures, wherein the active regions are electrically isolated and spaced apart from each other by the first isolation structures. 
     
     
         14 . The method of  claim 13 , wherein the first depth of the first trenches, the second depth of the second trenches and the third depth of the third trenches are less than a depth of the first isolation structures. 
     
     
         15 . The method of  claim 12 , wherein the third depth of the third trenches is greater than the first depth of the first trenches, and the first depth of the first trenches is greater than the second depth of the second trenches. 
     
     
         16 . The method of  claim 12 , wherein the forming the buried digit lines further comprises:
 forming a plurality of first doped regions m the substrate individually under the first trenches;   forming the buried digit lines in the first trenches, wherein top surfaces of the buried digit lines are lower than openings of the first trenches; and   forming a plurality of second isolation structures on the buried digit lines and filling the first trenches.   
     
     
         17 . The method of  claim 12 , wherein the forming the buried word lines further comprises:
 forming a plurality of first insulating layers individually in the third trenches, wherein top surfaces of the first insulating layers are lower than openings of the third trenches and higher than top surfaces of the buried digit lines;   forming the buried word lines on the first insulating layers in the third trenches, wherein top surfaces of the buried word lines are lower than the openings of the third trenches; and   forming a plurality of second insulating layers on the buried word lines and filling the third trenches.   
     
     
         18 . The method of  claim 17 , further comprising:
 forming a plurality of protecting spacers on the first insulating layers in the third trenches;   removing a portion of the first insulating layers and a portion of the substrate to form a plurality of curved recesses in the third trenches;   and forming the buried word lines in the curved recesses in the first trenches.   
     
     
         19 . The method of  claim 12 , further comprising forming a plurality of second doped regions in the active regions between the first trenches and the third trenches. 
     
     
         20 . The method of  claim 19 , further comprising a plurality of capacitors electrically connected to the second doped regions on the substrate.