Multiple sized bump bonds

Abstract

A semiconductor structure and methods for the creation of solder bumps configured to carry a signal and solder bumps configured for ground planes and/or mechanical connections as well as methods for increasing reliability of a chip package generally include formation of multiple sized bump bonds on under bump metallization patterns and/or pads of the same dimension. The signal carrying solder bumps are larger in terms of diameter and bump height than solder bumps configured for ground plane and/or mechanical connections.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a plurality of under bump metallization (UBM) layers overlying a pad, wherein each one of the UBMs have the same dimension;   a first solder bump on selected ones of the UBM layers; and   a second solder bump on the other ones of the UBM layers, wherein the first solder bumps have a first diameter (d1) and the second solder bumps have a second diameter (d2), wherein d1 is greater than d2, and wherein the first solder bumps are configured to carry signals between chips and the second solder bumps are configured for mechanical connection and/or ground connections.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising a passivation layer intermediate at least a portion of the pad and the UBM layer. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the diameter (d1) of the first solder bump is up to 20 percent larger than the diameter (d2) of the second solder bumps. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the diameter (d1) of the first solder bump is 1 to 2 standard deviations larger than the diameter (d2) of the second solder bumps. 
     
     
         5 . A semiconductor device, comprising:
 a plurality of under bump metallization (UBM) layers overlying a pad, wherein each one of the UBMs have the same dimension;   a first solder bump on selected ones of the UBM layers; and   a second solder bump on the other ones of the UBM layers, wherein the first solder bumps have a bump height (bh1) and the second solder bumps have a bump height (bh2), wherein bh1 is greater than bh2, and wherein the first solder bumps are configured to carry signals between chips and the second solder bumps are configured for mechanical connection and/or ground connections.   
     
     
         6 . The semiconductor device of  claim 5 , wherein bh2 is greater than 20 percent to less than 5 percent of bh2. 
     
     
         7 . The semiconductor device of  claim 5 , further comprising a passivation layer intermediate at least a portion of the pad and the UBM layer. 
     
     
         8 . The semiconductor device of  claim 5 , wherein the diameter (d1) of the first solder bump is up to 20 percent larger than the diameter (d2) of the second solder bumps. 
     
     
         9 . The semiconductor device of  claim 5 , wherein the diameter (d1) of the first solder bump is 1 to 2 standard deviations larger than the diameter (d2) of the second solder bumps. 
     
     
         10 - 23 . (canceled) 
     
     
         24 . A semiconductor device, comprising:
 one or more solder bumps configured for carrying a signal; and   one or more solder bumps configured for ground plane or mechanical connection, wherein the one or more solder bumps configured for carrying the signal have a greater bump height than the one or more solder bumps configured for ground plane or mechanical connection.   
     
     
         25 . The semiconductor device of  claim 24 , wherein one or more solder bumps configured for carrying a signal and one or more solder bumps configured for ground plane or mechanical connection are formed on an under bump metallization pattern, wherein each under bump metallization pattern has the same dimensions.