US2019194016A1PendingUtilityA1

Quantum computing assemblies

Assignee: INTEL CORPPriority: Sep 29, 2016Filed: Sep 29, 2016Published: Jun 27, 2019
Est. expirySep 29, 2036(~10.2 yrs left)· nominal 20-yr term from priority
H10W 70/63H10W 90/724H10W 72/07236H10W 72/07232H10W 72/252H10W 70/685H10W 70/611H10W 70/60H10W 90/00B82Y 10/00H01L 2224/16225H01L 29/7613H01L 23/538H01L 29/42376H01L 24/16H01L 2224/81203H01L 2224/81815H01L 2224/13101H01L 25/0655H01L 29/12H01L 29/66977H10D 62/812H10D 48/3835H10D 62/822H10D 62/814H10D 62/121H10D 64/518H10D 64/27H10D 62/81H10D 48/383H10D 30/402H10W 72/072H10W 72/20
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Claims

Abstract

Disclosed herein are quantum computing assemblies, as well as related computing devices and methods. For example, in some embodiments, a quantum computing assembly may include: a quantum device die to generate a plurality of qubits; a control circuitry die to control operation of the quantum device die; and a substrate; wherein the quantum device die and the control circuitry die are disposed on the substrate.

Claims

exact text as granted — not AI-modified
1 . A quantum computing assembly, comprising:
 a quantum device die to generate a plurality of qubits;   a control circuitry die to control operation of the quantum device die; and   a substrate;   wherein the quantum device die and the control circuitry die are disposed on the substrate.   
     
     
         2 . The quantum computing assembly of  claim 1 , wherein the substrate is a package substrate, and the quantum device die and the control circuitry die are included in a common package. 
     
     
         3 . The quantum computing assembly of  claim 1 , wherein the substrate is an interposer. 
     
     
         4 . The quantum computing assembly of  claim 1 , wherein the substrate is a printed circuit board. 
     
     
         5 . The quantum computing assembly of  claim 1 , wherein the quantum device die and the control circuitry die are included in a package-on-package structure. 
     
     
         6 . The quantum computing assembly of  claim 1 , wherein the substrate includes at least one microwave transmission line between the quantum device die and the control circuitry die. 
     
     
         7 . The quantum computing assembly of  claim 1 , wherein the substrate includes at least one conductive pathway between a face of the substrate to which the control circuitry die is coupled, and an opposing face of the substrate. 
     
     
         8 . The quantum computing assembly of  claim 1 , wherein the control circuitry die includes a processing device or a memory element. 
     
     
         9 . The quantum computing assembly of  claim 1 , wherein the quantum device die and the control circuitry die are each coupled to the substrate with solder connections. 
     
     
         10 . The quantum computing assembly of  claim 1 , wherein the quantum device die includes a plurality of gates, and the control circuitry die is to provide voltages to the plurality of gates through the substrate. 
     
     
         11 . The quantum computing assembly of  claim 1 , wherein the quantum device die includes one or more magnet lines, and the control circuitry die is to provide electrical pulses to the one or more magnet lines through the substrate. 
     
     
         12 . The quantum computing assembly of  claim 1 , wherein the control circuitry die includes a switching matrix for selecting one or more of the qubits to read or write. 
     
     
         13 . The quantum computing assembly of  claim 1 , wherein the qubits are quantum-dot-based qubits. 
     
     
         14 . The quantum computing assembly of  claim 1 , wherein the substrate includes electrical pathways between the quantum device die and the control circuitry die, and the electrical pathways include superconducting material. 
     
     
         15 . The quantum computing assembly of  claim 1 , further comprising:
 a memory device to store data generated by the control circuitry die during operation of the quantum device die.   
     
     
         16 . The quantum computing assembly of  claim 1 , further comprising:
 a wired or wireless network controller to receive and transmit data from the control circuitry die.   
     
     
         17 . A method of manufacturing a quantum computing assembly, including:
 providing a substrate, wherein the substrate includes one or more electrical pathways between a first set of contacts and a second set of contacts;   coupling a quantum device die to the first set of contacts such that the quantum device die is disposed on the substrate; and   coupling one or more control dies to the second set of contacts such that the one or more control dies are disposed on the substrate, wherein the control dies are to provide voltages to one or more components of the quantum device die through the one or more electrical pathways.   
     
     
         18 . The method of  claim 17 , wherein the one or more electrical pathways includes a coplanar waveguide, a strip line or a microstrip line. 
     
     
         19 . The method of  claim 17 , wherein the quantum device die is disposed on an intermediate structure, and coupling the quantum device die to the first set of contacts includes physically securing the intermediate structure on the first set of contacts. 
     
     
         20 . The method of  claim 17 , wherein one or more control dies are disposed on an intermediate structure, and coupling the one or more control dies to the second set of contacts includes physically securing the intermediate structure on the second set of contacts. 
     
     
         21 - 25 . (canceled)

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