Vertical memory devices

Abstract

A vertical memory device includes a substrate, a plurality of channels extending in a first direction substantially vertical to a top surface of the substrate, a plurality of gate lines surrounding a predetermined number of channels from among the channels, a plurality of common wirings electrically connected to the gate lines, and a plurality of signal wirings electrically connected to the gate lines via the common wirings. The gate lines are arranged and spaced apart from one another along the first direction. Each common wiring is electrically connected to a corresponding gate line at a same level of the corresponding gate line via a corresponding contact.

What is claimed is: 
     
         1 . A vertical memory device, comprising:
 a substrate;   a plurality of channels extending in a vertical direction with respect to a top surface of the substrate;   a plurality of gate lines surrounding a predetermined number of channels from among the channels, wherein the gate lines are arranged and spaced apart from one another along the vertical direction and a direction parallel to the top surface of the substrate, and the gate lines comprise a ground selection line (GSL), a plurality of word lines, and a string selection line (SSL) sequentially stacked on the top surface of the substrate;   a plurality of common wirings electrically connected to the gate lines, wherein each common wiring is electrically connected to corresponding gate lines at a same level from among the gate lines; and   a plurality of signal wirings electrically connected to the gate lines via the common wirings, wherein the signal wirings are distributed at a plurality of levels.   
     
     
         2 . The vertical memory device of  claim 1 , wherein the signal wirings are disposed over the common wirings, the signal wirings comprise first signal wirings and second signal wirings, and the first signal wirings are disposed at a different level than the second signal wirings. 
     
     
         3 . The vertical memory device of  claim 2 , wherein the first signal wirings are electrically connected to the GSL and lower word lines from among the word lines at a predetermined number of lower levels. 
     
     
         4 . The vertical memory device of  claim 3 , wherein the second signal wirings are electrically connected to upper word lines from among the word lines except for the lower word lines. 
     
     
         5 . The vertical memory device of  claim 4 , wherein the second signal wirings comprise a signal wiring electrically connected to the SSL. 
     
     
         6 . The vertical memory device of  claim 4 , wherein the second signal wirings are disposed over the first signal wirings. 
     
     
         7 . The vertical memory device of  claim 2 , further comprising:
 a plurality of first contacts connecting the gate lines and the common wirings;   a plurality of second contacts connecting the common wirings and the first signal wirings; and   a plurality of third contacts connecting the common wirings and the second signal wirings,   wherein one of the second contacts or one of the third contacts is disposed on each of the common wirings.   
     
     
         8 . The vertical memory device of  claim 1 , wherein the gate lines and the signal wirings extend in a first direction, and the common wirings extend in a second direction crossing the first direction. 
     
     
         9 . The vertical memory device of  claim 8 , wherein the common wirings overlap end portions of the gate lines and do not overlap the channels. 
     
     
         10 . A vertical memory device, comprising:
 a substrate;   a channel extending in a first direction substantially vertical to a top surface of the substrate;   a plurality of gate lines arranged and spaced apart from one another along the first direction, wherein the channel extends through the gate lines in the first direction;   a plurality of common wirings electrically connected to the gate lines;   a plurality of first contacts extending in the first direction, wherein a first end of each first contact is connected to one common wiring from among the common wirings, and a second end of each first contact is connected to a gate line from among the gate lines, wherein the second ends of the first contacts are disposed at different levels from one another;   a first signal wiring electrically connected to lower gate lines from among the gate lines via the common wirings; and   a second signal wiring electrically connected to upper gate lines from among the gate lines via the common wirings.   
     
     
         11 . The vertical memory device of  claim 10 , wherein the common wirings are disposed at a same level as one another, the first signal wiring is disposed over the common wirings, and the second signal wiring is disposed over the first signal wiring. 
     
     
         12 . The vertical memory device of  claim 10 ,
 wherein the gate lines are stacked along the first direction, and the gate lines extend in a second direction substantially parallel to the top surface of the substrate,   wherein the common wirings extend in a third direction substantially parallel to the top surface of the substrate and crossing the second direction, and the signal wirings extend in the second direction.