Semiconductor storage cube with enhanced sidewall planarity

Abstract

A semiconductor cube is disclosed including one or more highly planar vertical sidewalls on which to form a pattern of electrical traces. The semiconductor cube may be fabricated from a semiconductor cube assembly including a vertical semiconductor die stack and a pair of wire bond landing blocks. The vertical semiconductor die stack may be wire bonded off of first and second opposed edges to different levels of the first and second wire bond landing blocks. Once all wire bonds are formed, the semiconductor cube assembly may be encapsulated in mold compound. The mold compound may then be cut to separate the semiconductor die stack from the wire bond landing blocks, leaving the wire bonds exposed in a sidewall of the semiconductor cube.

We claim: 
     
         1 . A semiconductor cube, comprising:
 one or more semiconductor die, the one or more semiconductor die including die bond pads;   wire bonds having first ends affixed to the die bond pads;   a protective enclosure enclosing the one or more semiconductor die, the wire bonds having second ends, opposite the first ends, terminating at a sidewall of the protective enclosure; and   a pattern of electrical traces on the sidewall, electrically coupled to the second ends of the wire bonds terminating at the sidewall.   
     
     
         2 . The semiconductor cube of  claim 1 , wherein the one or more semiconductor die comprise a plurality of semiconductor die stacked with respect to each other. 
     
     
         3 . The semiconductor cube of  claim 2 , wherein the die bond pads comprise a column of die bond pads, the column of die bond pads comprising one die bond pad from each of the plurality of semiconductor die, and wherein the second ends of the wire bonds connected to the die bond pads in the column of die bond pads terminate in a column on the sidewall. 
     
     
         4 . The semiconductor cube of  claim 3 , wherein the pattern of electrical traces comprise a first electrical trace connecting the second ends of the wire bonds in the column on the sidewall. 
     
     
         5 . The semiconductor cube of  claim 1 , wherein the one or more semiconductor die comprise a plurality of flash memory die. 
     
     
         6 . The semiconductor cube of  claim 5 , further comprising a controller die electrically coupled to the plurality of flash memory die via the wire bonds and the pattern of electrical traces. 
     
     
         7 . The semiconductor cube of  claim 1 , wherein the one or more semiconductor die comprise a plurality of vertically stacked semiconductor die. 
     
     
         8 . The semiconductor cube of  claim 7 , further comprising a controller die mounted within the protective enclosure on top of the vertically stacked semiconductor die. 
     
     
         9 . The semiconductor cube of  claim 8 , wherein the controller die includes an electrical interconnect electrically connected to die bond pads on the controller die and terminating in the sidewall. 
     
     
         10 . The semiconductor cube of  claim 9 , wherein the pattern of electrical traces electrically connect a second end of a wire bond from the one or more semiconductor die with the electrical interconnects from the controller die at the sidewall. 
     
     
         11 . The semiconductor cube of  claim 9 , wherein the electrical interconnects comprise a pad. 
     
     
         12 . The semiconductor cube of  claim 9 , wherein the electrical interconnects comprise a wire bond. 
     
     
         13 . The semiconductor cube of  claim 1 , further comprising electrical connectors on a surface of the semiconductor cube adjacent the sidewall configured to affix the semiconductor cube to a host device. 
     
     
         14 . The semiconductor cube of  claim 13 , wherein the electrical connectors comprises an array of solder bumps or balls. 
     
     
         15 . A semiconductor cube, comprising:
 a plurality of stacked semiconductor die comprising a first set of die bond pads;   wire bonds having first ends affixed to the first set of die bond pads;   a controller die comprising a second set of die bond pads;   electrical interconnects coupled to the second set of die bond pads;   a protective enclosure enclosing the one or more semiconductor die, the wire bonds having a second end, opposite the first end, terminating at a sidewall of the protective enclosure, and the electrical interconnects having a portion terminating at the sidewall; and   a pattern of electrical traces on the sidewall in physical contact with the second ends of the wire bonds terminating at the sidewall and in physical contact with the portion of the electrical interconnects terminating at the sidewall.   
     
     
         16 . The semiconductor cube of  claim 15 , wherein the electrical interconnects comprise pads terminating at the sidewall. 
     
     
         17 . The semiconductor cube of  claim 15 , wherein the electrical interconnects comprise wire bonds terminating at the sidewall. 
     
     
         18 . The semiconductor cube of  claim 15 , wherein the pattern of electrical traces electrically connect the wire bonds from the plurality of semiconductor die with the electrical interconnects from the controller die. 
     
     
         19 . The semiconductor cube of  claim 15 , wherein the die bond pads comprise a column of die bond pads, the column of die bond pads comprising one die bond pad from each of the plurality of semiconductor die, and wherein the second ends of the wire bonds connected to the die bond pads in the column of die bond pads terminate in a row on the sidewall. 
     
     
         20 . The semiconductor cube of  claim 19 , wherein the pattern of electrical traces comprise a first electrical trace connecting the second ends of the wire bonds in the row on the sidewall. 
     
     
         21 . The semiconductor cube of  claim 20 , wherein the first electrical trace connects with the portion of the electrical interconnects from the controller die at the sidewall. 
     
     
         22 . A method of fabricating a semiconductor cube comprising a plurality of stacked semiconductor die and wire bonds having a first end coupled to the plurality of semiconductor die and a second end, opposite the first end, terminating at a sidewall of the semiconductor cube, the method comprising:
 (a) forming wire bonds between a semiconductor die of the stacked semiconductor die and a wire bond landing block;   (b) encapsulating the stacked semiconductor die, wire bonds and at least a portion of the wire bond landing block in a protective enclosure to form a semiconductor cube assembly;   (c) cutting the semiconductor cube assembly to separate the stacked semiconductor die from the wire bond landing block and severing the wire bonds in a sidewall of the semiconductor cube; and   (d) forming electrical traces on the sidewall interconnecting the severed wire bonds.   
     
     
         23 . The method of  claim 22 , further comprising the steps of:
 building a first layer of the stacked semiconductor die and wire bond landing block by mounting a first semiconductor die adjacent a first layer of the wire bond landing block;   forming the wire bonds of the step (a) on the first layer;   encasing the wire bonds in a film; and   building a second layer of the stacked semiconductor die and wire bond landing block on top of the film.   
     
     
         24 . A semiconductor cube, comprising:
 one or more semiconductor die, the one or more semiconductor die including die bond pads;   wire bond means having first ends affixed to the die bond pads;   a protective enclosure means enclosing the one or more semiconductor die, the wire bond means having second ends, opposite the first ends, terminating at a sidewall of the protective enclosure means; and   electrical trace means on the sidewall, electrically coupled to the second ends of the wire bond means terminating at the sidewall.