Cooperative triggering

Abstract

There is disclosed in an example a processor, having: a front end including circuitry to decode instructions from an instruction stream; a data cache unit including circuitry to cache data for the processor; and a core triggering block (CTB) to provide integration between two or more different debug capabilities.

What is claimed is: 
     
         1 . A processor, comprising:
 a front end including circuitry to decode instructions from an instruction stream;   a data cache unit including circuitry to cache data for the processor; and   a core triggering block (CTB) to provide coordination between two or more monitoring capabilities during a software execution, wherein the CTB is to:
 provide a function during the software execution based on a first trigger input of two or more trigger inputs associated with the two or more monitoring capabilities. 
   
     
     
         2 . The processor of  claim 1 , wherein the two or more monitoring capabilities include a performance monitoring capability and a debug capability. 
     
     
         3 . The processor of  claim 1 , wherein the first trigger input is associated with a first monitoring capability and the function is associated with a second monitoring capability. 
     
     
         4 . The processor of  claim 1 , wherein the function includes logging or tracing data to an on-chip visibility buffer, and wherein the CTB is further to flush the on-chip visibility buffer to main memory. 
     
     
         5 . The processor of  claim 1 , wherein the function includes logging or tracing data. 
     
     
         6 . The processor of  claim 5 , wherein the CTB is to provide the logging or tracing on an instruction boundary. 
     
     
         7 . The processor of  claim 5 , wherein the CTB is to provide the logging or tracing without interrupting the software execution. 
     
     
         8 . The processor of  claim 1 , wherein the first trigger input includes debug register matching logic, and wherein the function includes logging packet data with an on-chip performance tracer. 
     
     
         9 . The processor of  claim 8 , wherein the packet data includes an instruction pointer (IP) and a data linear address (DLA) of an access to a variable or data structure. 
     
     
         10 . The processor of  claim 1 , further comprising an off-die interface to interoperate with an uncore block or peripheral device. 
     
     
         11 . The processor of  claim 1 , wherein the CTB is provided primarily in hardware. 
     
     
         12 . A core triggering block (CTB), comprising circuitry to:
 communicatively couple to a front end of a processor, the front end having instruction decode circuitry;   communicatively couple to a data cache having circuitry to cache data for the processor;   coordinate two or more monitoring capabilities of a microprocessor during a software execution; and   provide, during the software execution, a function associated with a first monitoring capability based on a first trigger input associated with a second monitoring capability.   
     
     
         13 . The CTB of  claim 12 , wherein the two or more monitoring capabilities include a performance monitoring capability and a debug capability. 
     
     
         14 . The CTB of  claim 12 , wherein the function includes a data address trace performed by a performance tracer (PT). 
     
     
         15 . The CTB of  claim 12 , further comprising circuitry to communicatively couple to an on-chip visibility buffer, wherein coordinating the two or more monitoring capabilities comprises writing logging or tracing data to the on-chip visibility buffer. 
     
     
         16 . The CTB of  claim 12 , wherein the function includes a logging or tracing function to be provided without interrupting the software execution. 
     
     
         17 . The CTB of  claim 12 , wherein the circuitry is to provide a second function based on at least two trigger inputs associated with at least one monitoring capability of the two or more monitoring capabilities. 
     
     
         18 . A method of providing visibility features for a processor, comprising:
 communicatively coupling to a front end having instruction decode circuitry;   communicatively coupling to a data cache having circuitry to cache data for the processor;   coordinating two or more monitoring capabilities of the processor within a core triggering block (CTB) during a software execution; and   providing, by the CTB, a function during the software execution based on a first trigger input of two or more trigger inputs associated with the two or more monitoring capabilities.   
     
     
         19 . The method of  claim 18 , wherein the two or more monitoring capabilities include a performance monitoring capability and a debug capability. 
     
     
         20 . The method of  claim 18 , wherein the function includes logging or tracing packet data.